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PDF UG01 Data sheet ( Hoja de datos )
| Número de pieza | UG01 | |
| Descripción | (UG01 - UG09) 0.6um ULC | |
| Fabricantes | Temic | |
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Hay una vista previa y un enlace de descarga de UG01 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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www.DataSheet4U.com
0.6µm ULC Series
UG Series
Description
The UG series of ULCs is well suited for conversion of
medium- to-large sized CPLDs and FPGAs. Devices are
implemented in high-performance CMOS technology
with 0.6-µm (drawn) channel lengths, and are capable of
supporting flip-flop toggle rates of 350 MHz, operating
clock frequencies up to 150 MHz and input to output
delays as fast as 5 ns.
The architecture of the UG series allows for efficient
conversion of many PLD architectures and FPGA
device types. A compact RAM cell, along with the large
number of available gates allows the implementation of
RAM in FPGA architectures that support this feature, as
well as JTAG boundary-scan and scan-path testing.
Conversion to the UG series of ULC can provide a
significant reduction in operating power when
compared to the original PLD or FPGA. This is
especially true when compared to many PLD and CPLD
architecture devices, which typically consume 100 mA
or more even when not being clocked. The UG series has
a very low standby consumption of 0.4 nA/gate
typically, which would yield a standby current of 4 mA
on a 10,000 gate design. Operating consumption is a
strict function of clock frequency, which typically
results in a power reduction of 50% to 90% depending
on the device being compared.
The UG series provides several options for output
buffers, including a variety of drive levels up to 24 mA.
Schmitt trigger inputs are also an option. A number of
techniques are used for improved noise immunity and
reduced EMC emissions, including: several
independent power supply busses and internal
decoupling for isolation; slew rate limited outputs are
also available as required.
The UG series is designed to allow conversions of high
performance 3.3V devices as well as 5.0V devices.
Support of mixed supply conversions is also possible,
allowing optimal trade-offs between speed and power
consumption.
Features
D High performance ULC family suitable for
medium- to large-sized CPLDs and FPGAs
D Conversions to over 200,000 FPGA gates
D Pin counts to over 300 pins
D Any pin-out matched due to limited number of
dedicated pads
D Advanced 0.6-µm (drawn)/0.45-µm (effective)
feature size
D Triple-layer or dual-layer metal CMOS
technology
D High speed performance:
– 250-ps typical cell delay
– 350-MHz toggle rate
D Full range of packages: DIP, SOIC, LCC/PLCC,
PQFP/TQFP, PGA/PPGA
D 3.3V and/or 5.0V operation.
D Low quiescent current: 0.4 nA/gate
D Available in commercial, industrial, automotive,
military and space grades.
www.DataSheet4U.com
Rev. B – 25 May. 98
5–1
1 page  
www.DataSheet4U.com
UG Series
Derating Factors: tP = KP x Kt x KV x tNOMINAL
Process
Process
KP
Ambient Temperature _C
Best
0.82
TA –55 –40
0
KT 0.74 0.79 0.92
Supply Voltage
VDD 2.7 3 3.13 3.3
KV 1.89 1.66 1.58 1.49
External Timing Characteristics
(Over the Operating Range)
These timing parameters are provided for information
Nominal
1.00
Worst
1.28
25 70 85 125
1.00 1.15 1.20 1.32
3.47 3.6 4 4.5 4.75 5 5.25 5.5
1.41 1.35 1.23 1.1 1.05 1 0.96 0.93
only. Actual pin-to-pin timing characteristics
guaranteed for ULCs are determined by the original
FPGA or PLD data sheet plus any specific parameters
that are agreed to separately by TEMIC.
Parameter
Symbol
Propagation Time
tPD
Clock Delay Time
Hold Time
Output Enable Time
tCO
tH
tEN
Base Part
UG01
UG04–UG09
UG14–UG20
UG33–UG90
UG120–UG140
UG01
UG04–UG09
UG14–UG20
UG33–UG90
UG120–UG140
UG01
UG04–UG09
UG14–UG20
UG33–UG90
UG120–UG140
SSO Min
32
50
100
220
300
0.0
32
50
100
220
300
Max
Unit
Typ Max
5.0 7.5
6.0 9.0
7.0 10.5
8.5 13.0
9.5 14.5
6.5 10.0
7.5 11.5
8.5 13.0
ns
10.0 15.0
11.0 16.5
6.5 10.0
7.5 11.5
8.5 13.0
10.0 15.0
11.0 16.5
www.DataSheet4U.com
Rev. B – 25 May. 98
5–5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet UG01.PDF ] | |
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