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2S80TD の電気的特性と機能

2S80TDのメーカーはAnalog Devicesです、この部品の機能は「AD2S80A」です。


製品の詳細 ( Datasheet PDF )

部品番号 2S80TD
部品説明 AD2S80A
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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2S80TD Datasheet, 2S80TD PDF,ピン配置, 機能
a
Variable Resolution, Monolithic
Resolver-to-Digital Converter
AD2S80A
FEATURES
Monolithic (BiMOS ll) Tracking R/D Converter
40-Lead DIP Package
44-Terminal LCC Package
10-,12-,14-, and 16-Bit Resolution Set by User
Ratiometric Conversion
Low Power Consumption: 300 mW Typ
Dynamic Performance Set by User
High Max Tracking Rate 1040 RPS (10 Bits)
Velocity Output
Industrial Temperature Range Versions
Military Temperature Range Versions
ESD Class 2 Protection (2,000 V Min)
/883 B Parts Available
APPLICATIONS
DC Brushless and AC Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
Military Servo Control
GENERAL DESCRIPTION
The AD2S80A is a monolithic 10-, 12-, 14-, or 16-bit tracking
resolver-to-digital converter contained in a 40-lead DIP or 44-
terminal LCC ceramic package. It is manufactured on a BiMOS
II process that combines the advantages of CMOS logic and
bipolar high accuracy linear circuits on the same chip.
The converter allows users to select their own resolution and dynamic
performance with external components. This allows the users great
flexibility in defining the converter that best suits their system
requirements. The converter allows users to select the resolution
to be 10, 12, 14, or 16 bits and to track resolver signals rotating
at up to 1040 revs per second (62,400 rpm) when set to 10-bit
resolution.
The AD2S80A converts resolver format input signals into a
parallel natural binary digital word using a ratiometric tracking
conversion method. This ensures high-noise immunity and toler-
ance of lead length when the converter is remote from the resolver.
The 10-, 12-, 14- or 16-bit output word is in a three-state digital
logic available in 2 bytes on the 16 output data lines. BYTE
SELECT, ENABLE and INHIBIT pins ensure easy data trans-
fer to 8- and 16-bit data buses, and outputs are provided to
allow for cycle or pitch counting in external counters.
An analog signal proportional to velocity is also available and
can be used to replace a tachogenerator.
The AD2S80A operates over 50 Hz to 20,000 Hz reference
frequency.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
SIN I/P
SIG GND
COS I/P
ANALOG
GND
RIPPLE
CLK
DATA
LOAD
+12V
–12V
AD2S80A
A1 A3
SEGMENT
SWITCHING
A2
R-2R
DAC
PHASE
SENSITIVE
DETECTOR
16-BIT UP/DOWN COUNTER
VCO DATA
TRANSFER
LOGIC
OUTPUT DATA LATCH
INTEGRATOR
O/P
VCO I/P
16 DATA BITS
PRODUCT HIGHLIGHTS
Monolithic. A one chip solution reduces the package size
required and increases the reliability.
Resolution Set by User. Two control pins are used to select
the resolution of the AD2S80A to be 10, 12, 14, or 16 bits allowing
the user to use the AD2S80A with the optimum resolution for
each application.
Ratiometric Tracking Conversion. Conversion technique
provides continuous output position data without conversion
delay and is insensitive to absolute signal levels. It also provides
good noise immunity and tolerance to harmonic distortion on
the reference and input signals.
Dynamic Performance Set by the User. By selecting exter-
nal resistor and capacitor values the user can determine bandwidth,
maximum tracking rate and velocity scaling of the converter to
match the system requirements. The external components
required are all low cost preferred value resistors and capacitors,
and the component values are easy to select using the simple
instructions given.
Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization in servo controls and velocity feedback data.
Low Power Consumption. Typically only 300 mW.
Military Product. The AD2S80A is available processed in
accordance with MIL-STD-883B, Class B.
MODELS AVAILABLE
Information on the models available is given in the section
“Ordering Information.”
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
©Analog Devices, Inc., 1986–2015

1 Page





2S80TD pdf, ピン配列
AD2S80A–SPECIFICATIONS (typical at 25؇C unless otherwise noted)
Parameter
SIGNAL INPUTS
Frequency
Voltage Level
Input Bias Current
Input Impedance
Maximum Voltage
REFERENCE INPUT
Frequency
Voltage Level
Input Bias Current
Input Impedance
CONTROL DYNAMICS
Repeatability
Allowable Phase Shift
Tracking Rate
Bandwidth1
ACCURACY
Angular Accuracy
Monotonicity
Missing Codes (16-Bit Resolution)
VELOCITY SIGNAL
Linearity
Reversion Error
DC Zero Offset2
DC Zero Offset Tempco
Gain Scaling Accuracy
Output Voltage
Dynamic Ripple
Output Load
INPUT/OUTPUT PROTECTION
Analog Inputs
Analog Outputs
DIGITAL POSITION
Resolution
Output Format
Load
INHIBIT3
Sense
Time to Stable Data
ENABLE3
ENABLE Time
BYTE SELECT3
Sense
LOGIC LO
Time to Data Available
SHORT CYCLE INPUTS
SC1 SC2
00
01
10
11
Conditions
(Signals to Reference)
10 Bits
12 Bits
14 Bits
16 Bits
User Selectable
A, J, S
B, K, T
L, U
Guaranteed Monotonic
A, B, J, K, S, T
L, U
Over Full Range
Min
50
1.8
1.0
50
1.0
1.0
–10
1 mA Load
Mean Value
±8
Overvoltage Protection
Short Circuit O/P Protection
10, 12, 14, and 16
Bidirectional Natural Binary
± 5.6
Logic LO to Inhibit
Logic LO Enables Position
Output. Logic HI Outputs in
High Impedance State
MS Byte DB1–DB8,
LS Byte DB9–DB16
LS Byte DB1–DB8,
LS Byte DB9–DB16
Internally Pulled High
(100 k) to +VS
10 Bit
12 Bit
14 Bit
16 Bit
35
60
Typ
2.0
60
60
±1
±1
–22
±9
±8
±8
Max
20,000
2.2
150
8
20,000
8.0
150
1
+10
1040
260
65
16.25
Unit
Hz
V rms
nA
M
V pk
Hz
V pk
nA
M
LSB
Degrees
rps
rps
rps
rps
؎8 +1 LSB
؎4 +1 LSB
؎2 +1 LSB
4
1
؎3
±2
6
± 10
± 10.5
1.5
1.0
± 10.4
arc min
arc min
arc min
Codes
Code
% FSD
% FSD
mV
µV/°C
% FSD
V
% rms O/P
k
V
mA
3 LSTTL
600 ns
110 ns
140 ns
–2– REV. D


3Pages


2S80TD 電子部品, 半導体
AD2S80A
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage (+VS, –VS) . . . . . . . . . ± 12 V dc ± 10%
Power Supply Voltage VL . . . . . . . . . . . . . . . . . . . 5 V dc ± 10%
Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ± 10%
Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak
Signal and Reference Harmonic Distortion . . . . . . . 10% (max)
Phase Shift Between Signal and Reference . . . ± 10 Degrees (max)
Ambient Operating Temperature Range
Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C
Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C
ABSOLUTE MAXIMUM RATINGSl (with respect to GND)
+VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc
+VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS
Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc
Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS
Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS
VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW
Operating Temperature
Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C
Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C
θJC3 (40-Lead DIP 883 Parts Only) . . . . . . . . . . . . . . . 11°C/W
θJC3 (44-Terminal LCC 883 Parts Only) . . . . . . . . . . . 10°C/W
Storage Temperature (All Grades) . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
CAUTION NOTES:
1Absolute Maximum Ratings are those values beyond which damage to the device
may occur.
2Correct polarity voltages must be maintained on the +VS and –VS pins.
3With reference to Appendix C of MIL-M-38510.
Bit Weight Table
Binary
Bits (N)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Resolution Degrees
(2N) /Bit
Minutes
/Bit
Seconds
/Bit
1 360.0
2 180.0
4 90.0
8 45.0
16 22.5
21600.0
10800.0
5400.0
2700.0
1350.0
1296000.0
648000.0
324000.0
162000.0
81000.0
32 11.25
675.0
40500.0
64 5.625
337.5
20250.0
128
2.8125
168.75
10125.0
256
1.40625
84.375
5062.5
512
0.703125
42.1875
2531.25
1024
2048
4096
8192
116384
0.3515625
0.1757813
0.0878906
0.0439453
0.0219727
21.09375
10.546875
5.273438
2.636719
1.318359
1265.625
632.8125
316.40625
158.20313
79.10156
32768
65536
131072
262144
0.0109836
0.0054932
0.0027466
0.0013733
0.659180
0.329590
0.164795
0.082397
39.55078
19.77539
9.88770
4.94385
PIN CONFIGURATIONS
DIP (D) Package
REFERENCE I/P 1
DEMOD I/P 2
40 DEMOD O/P
39 INTEGRATOR O/P
AC ERROR O/P 3
38 INTEGRATOR I/P
COS 4
37 VCO I/P
ANALOG GND 5
SIGNAL GND 6
36 VS
35 RIPPLE CLK
SIN 7
+VS 8
34 DIRECTION
33 BUSY
MSB DB1 9
32 DATA LOAD
DB2 10 AD2S80A 31 SC2
TOP VIEW
DB3 11 (Not to Scale) 30 SC1
DB4 12
29 DIGITAL GND
DB5 13
28 INHIBIT
DB6 14
27 BYTE SELECT
DB7 15
26 ENABLE
DB8 16
DB9 17
25 VL
24 DB16 LSB
DB10 18
23 DB15
DB11 19
22 DB14
DB12 20
21 DB13
6 5 4 3 2 1 44 43 42 41 40
LCC (E) Package
SIN 7
+VS 8
NC 9
MSB DB1 10
DB2 11
DB3 12
DB4 13
DB5 14
DB6 15
DB7 16
DB8 17
AD2S80A
TOP VIEW
(Not to Scale)
39 VS
38 RIPPLE CLOCK
37 DIRECTION
36 BUSY
35 DATA LOAD
34 NC
33 SC2
32 SC1
31 DIGITAL GND
30 INHIBIT
29 NC
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
PIN DESIGNATIONS
MNEMONIC
REFERENCE I/P
DEMOD I/P
AC ERROR O/P
COS
ANALOG GROUND
SIGNAL GROUND
SIN
+VS
DB1–DB16
VL
ENABLE
BYTE SELECT
INHIBIT
DIGITAL GROUND
SC1–SC2
DATA LOAD
BUSY
DIRECTION
RIPPLE CLOCK
–VS
VCO I/P
INTEGRATOR I/P
INTEGRATOR O/P
DEMOD O/P
DESCRIPTION
REFERENCE SIGNAL INPUT
DEMODULATOR INPUT
RATIO MULTIPLIER OUTPUT
COSINE INPUT
POWER GROUND
RESOLVER SIGNAL GROUND
SINE INPUT
POSITIVE POWER SUPPLY
PARALLEL OUTPUT DATA
LOGIC POWER SUPPLY
LOGIC Hl-OUTPUT DATA IN HIGH IMPEDANCE
STATE, LOGIC LO PRESENTS DATA TO THE
OUTPUT LATCHES
LOGIC Hl-MOST SIGNIFICANT BYTE TO DB1–DB8
LOGIC LO-LEAST SlGNlFlCANT BYTE TO DB1–DB8
LOGIC LO INHIBITS DATA TRANSFER TO
OUTPUT LATCHES
DlGITAL GROUND
SELECT CONVERTER RESOLUTION
LOGIC LO DB1–DB16 INPUTS LOGIC Hl DB1–D16
OUTPUTS
CONVERTER BUSY, DATA NOT VALID WHILE
BUSY Hl
LOGIC STATE DEFINES DIRECTION
OF INPUT SIGNAL ROTATION
POSITIVE PULSE WHEN CONVERTER OUTPUT
CHANGES FROM 1S TO ALL 0S OR VICE VERSA
NEGATIVE POWER SUPPLY
VCO INPUT
INTEGRATOR INPUT
INTEGRATOR OUTPUT
DEMODULATOR OUTPUT
REV. D
–5–

6 Page



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部品番号部品説明メーカ
2S80TD

AD2S80A

Analog Devices
Analog Devices


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