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Z-380 の電気的特性と機能

Z-380のメーカーはZilogです、この部品の機能は「Microprocessor」です。


製品の詳細 ( Datasheet PDF )

部品番号 Z-380
部品説明 Microprocessor
メーカ Zilog
ロゴ Zilog ロゴ 




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Z-380 Datasheet, Z-380 PDF,ピン配置, 機能
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ZILOG
PRODUCT SPECIFICATION
MICROPROCESSOR
FEATURES
s Static CMOS Design with Low-Power Standby Mode
Option
s 32-Bit Internal Data Paths and ALU
s Operating Frequency
- DC-to-18 MHz at 5V
- DC-to-10 MHz at 3.3V
s Enhanced Instruction Set that Maintains Object-Code
Compatibility with Z80® and Z180Microprocessors
s 16-Bit (64K) or 32-Bit (4G) Linear Address Space
s 16-Bit Data Bus with Dynamic Sizing
Z380
MICROPROCESSOR
s Two-Clock Cycle Instruction Execution Minimum
s Four Banks of On-Chip Register Files
s Enhanced Interrupt Capabilities, Including
16-Bit Vector
s Undefined Opcode Trap for Z380Instruction Set
s On-Chip I/O Functions:
- Six-Memory Chip Selects with Programmable Waits
- Programmable I/O Waits
- DRAM Refresh Controller
s 100-Pin QFP Package
GENERAL DESCRIPTION
The Z380Microprocessor is an integrated high-
performance microprocessor with fast andefficientthrough-
put and increased memory addressing capabilities. The
Z380offers a continuing growth path for present Z80-or
Z180-based designs, while maintaining Z80® CPU and
Z180® MPU object-code compatibility. The Z380MPU
enhancements include an improved 280 CPU, expanded
4-Gbyte space and flexible bus interface timing.
An enhanced version of the Z80 CPU is key to the Z380
MPU. The basic addressing modes of the Z80 micropro-
cessor have been augmented as follows: Stack Pointer
Relative loads and stores, 16-bit and 24-bit indexed off-
sets, and more flexible Indirect Register addressing, with
all of the addressing modes allowing access to the entire
32-bit address space. Additions made to the instruction
set, include a full complement of 16-bit arithmetic and
logical operations, 16-bit I/O operations, multiply and
divide, plus a complete set of register-to-register loads
and exchanges.
The expanded basic register file of the Z80 MPU micropro-
cessor includes alternate register versions of the IX and IY
registers. There are four sets of this basic Z80 micropro-
cessor register file present in the Z380 MPU, along with the
necessary resources to manage switching between the
different register sets. All of the register-pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.
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Z-380 pdf, ピン配列
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ZILOG
MICROPROCESSOR
A5
A4
A3
A2
A1
A0
VSS
VDD
VSS
VDD
/TREFR
/TREFA
/TREFC
/BHEN
/BLEN
/MRD
/MWR
/MSIZE
/WAIT
BUSCLK
IOCLK
/M1
/IORQ
/IORD
CLKI
CLKO
/IOWR
VSS
VDD
VSS
100
1
95
90
85 80
2
5
75
10
Z380
15 100-Pin QFP
70
65
20
60
25
55
30 35 40 45 50
A23
A24
A25
A26
A27
A28
A29
A30
A31
VSS
VDD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDD
VSS
Figure 2. 100-Pin QFP Pin Assignments
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PS010001-0301


3Pages


Z-380 電子部品, 半導体
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ZILOG
PIN DESCRIPTION (Continued)
Pin
Names
CLKI
CLKO
CLKSEL
BUSCLK
IOCLK
A31-A0
D15-D0
/TREFR,/TREFA,
/TREFC
/MRD,/MWR
/BHEN,/BLEN
/LMCS,/UMCS,
/MCS3-MCS0
/MSIZE,/WAIT
/HALT,/STNBY
/M1,/INTAK
/IORQ,/IORD,
/IOWR
/BREQ
/BACK
/NMI,/INT3-/INT0
/RESET
/EV
VDD
VSS
Table 1. Z380 MPU Pin Conditioning Characteristics
Operation Mode Conditions
Normal
/BREQ=1,/BACK=1,
/EV=NC
Bus Relinquish
/BREQ=0,/BACK=0,
/EV=NC
Input
Output/No Connection
Input
Output
Output
Output
Input
Output/No Connection
Input
Output
Output
Tri-state
Input/Output
Output
Tri-state
Tri-state
Output
Output
Output
Tri-state
Tri-state
Tri-state
Input
Output
Output
Output
Input
Output
Input
Input
No Connection
Power
Ground
Input
Output
Output
Tri-state
Input
Output
Input
Input
No Connection
Power
Ground
MICROPROCESSOR
Evaluation
Input
No Connection
Input
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Input
Tri-state
Tri-state
Tri-state
Input
Tri-state
Input
Input
Input
Power
Ground
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PS010001-0301

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
Z-380

Microprocessor

Zilog
Zilog


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