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PDF IXP1240 Data sheet ( Hoja de datos )
| Número de pieza | IXP1240 | |
| Descripción | Network Processor | |
| Fabricantes | Intel | |
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Intel® IXP1240 Network Processor
Specification Update
March 2004
Notice: The IXP1240 may contain design defects or errors known as errata. Characterized errata that
may cause the IXP1240’s behavior to deviate from published specifications are documented in this
specification update.
Part Number: 278505-005
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1 page  
Preface
Intel® IXP1240 Network Processor
Preface
This document is an update to the specifications contained in the Related Documents table below.
This document is a compilation of device and documentation errata, specification clarifications and
changes. It is intended for hardware system manufacturers and software developers of applications,
operating systems, or tools.
We have endeavored to include all documented errata in the consolidation process, however, we
make no representations or warranties concerning the completeness of this Specification Update.
Information types defined in Nomenclature are consolidated into the specification update and are
no longer published in other documents.
This document may also contain information that was not previously published.
Related Documents
Title
IXP1240 Network Processor Datasheet
IXP1200 Network Processor Family Hardware Reference Manual
Part Number
278405
278303
Specification Update
5
5 Page 
Errata
Intel® IXP1240 Network Processor
Errata
1.
Problem:
SRAM Registers
Reads of the SRAM_BOOT_CONFIG and SRAM_SLOWPORT_CONFIG registers return the
two inner bytes out of order.
SRAM_BOOT_CONFIG:
Written as: BRWA BCEA BRWD BCED
Read as: BRWA BRWD BCEA BCED
Implication:
Workaround:
Status:
SRAM_SLOWPORT_CONFIG:
Written as: SRWA SCEA SRWD SCED
Read as: SRWA SRWD SCEA SCED
Bytes are read out of order.
Software that reads these registers needs to put the bytes in the correct order.
NoFix
2.
Problem:
Implication:
Workaround:
Status:
CSR Access Using PCI Memory Cycles
The 128 byte window size is not supported. All other window sizes are valid. The
CSR_BASE_ADDR_MASK[18] may only be set to 1, preventing the 128 byte window size from
being selected. All other sizes are supported.
A 128 byte window size is not valid.
Use a different PCI window size.
NoFix
3.
Problem:
Implication:
Workaround:
Status:
PCI_DMA Instruction
The Microengine PCI_DMA instruction SDRAM address operand is misaligned.
Incorrect addressing occurs if the address operand is not shifted.
The SDRAM address operand of the PCI_DMA instruction requires a 1-bit right shift for proper
quadword addressing. For example, the address of a Descriptor Pointer located at SDRAM address
0x1000 should be right-shifted 1 bit with the resulting operand value being 0x0800, as follows:
; fix address of SDRAM Descriptor Pointer
immed[tmp1, 0x1000]
alu[DESC_ADDR,--,B,tmp1,>>1]
; issue DMA request
pci_dma[DESC_ADDR, 0, any_queue]
NoFix
Specification Update
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet IXP1240.PDF ] | |
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