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PDF IS61LF51218 Data sheet ( Hoja de datos )
| Número de pieza | IS61LF51218 | |
| Descripción | (IS61LF25632 / IS61LF25636 / IS61LF51218) 256Kx32 Synchronous Flow-through Static RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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( DataSheet : www.DataSheet4U.com )
IS61LF25632T/D/J
ISSIIS61LF25636T/D/J IS61LF51218T/D/J
®
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
OCTOBER 2002
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global
Write
• Clock controlled, registered address, data
and control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Power Supply
+ 3.3V VDD
+ 3.3V or 2.5V VDDQ (I/0)
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• J version (PBGA Package with JTAG)
• D version (two chip selects)
• JTAG Boundary Scan for PBGA.
DESCRIPTION
The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are
high-speed, low-power synchronous static RAMs designed to
provide a burstable, high-performance and memories for
commucation and networking applications. The IS61LF25632
is organized as 262,144 words by 32 bits and the IS61LF25636
is organized as 262,144 words by 36 bits. The IS61LF51218 is
organized as 524,288 words by 18 bits. Fabricated with ISSI's
advanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers that are controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. Byte
write operation is performed by using byte write enable
(BWE).input combined with one or more individual byte write
signals (BWx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear
burst is achieved when this pin is tied LOW. Interleave burst is
achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
6.5 7.5
6.5 7.5
7.5 8.5
133 117
Units
ns
ns
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
www.DataSheet4U.com
1
1 page  
IS61LF25632T/D/J
IS61LF25636T/D/J IS61LF51218T/D/J
PIN CONFIGURATION
100-pin TQFP (T Version)
100-Pin TQFP (D Version)
ISSI ®
DQPc
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
DQPa
256K x 36
256K x 36
PIN DESCRIPTIONS
A0, A1
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
TMS, TDI
TCK, TDO
GW
CE, CE2
OE
DQa-DQd
MODE
VDD
GND
VDDQ
ZZ
DQPa-DQPd
JTAG Boundry Scan Pins
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V or 2.5V
Snooze Enable
Parity Data I/O
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
10/06/02
5
5 Page 
IS61LF25632T/D/J
IS61LF25636T/D/J IS61LF51218T/D/J
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
Industrial
–40°C to +85°C
VDD
3.3V, +10%, –5%
3.3V, +10%, –5%
VDDQ
2.375–3.6V
2.375–3.6V
ISSI ®
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
ILI Input Leakage Current
ILO Output Leakage Current
Test Conditions
IOH = –1.0 mA, VDDQ = 2.5V
IOH = –4.0 mA, VDDQ = 3.3V
IOL = 1.0 mA, VDDQ = 2.5V
IOL = 8.0 mA, VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
GND ≤ VIN ≤ VDDQ(2)
GND ≤ VOUT ≤ VDDQ, OE = VIH
Com.
Ind.
Com.
Ind.
Min.
2.0
2.4
—
—
1.7
2.0
–0.3
–0.3
–5
–5
–5
–5
Max.
—
—
0.4
0.4
VDD + 0.3
VDD + 0.3
0.7
0.8
5
5
5
5
Unit
V
V
V
V
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
6.5 7.5
Max. Max. Unit
ICC AC Operating
Device Selected,
Supply Current All Inputs < VIL or > VIH
OE = VIH, ZZ < VIL
Cycle Time ≥ tKC min.
Com.
Ind.
110 100 mA
120 110 mA
ISB Standby Current Device Deselected,
VDD = Max.,
All Inputs < VIL or > VIH
ZZ < VIL, f = fmax
Com.
Ind.
55 55 mA
60 60 mA
ISBI Standby Current Device Deselected,
Com.
CMOS Input
VDD = Max.,
Ind.
VIN ≤ GND + 0.2V or ≥ VDD -0.2V
f=0
30 30 mA
40 40 mA
Notes:
1. The MODE pin should be tied to VDD or GND. It exhibits ±30 µA maximum leakage current when tied to< GND + 0.2V
or ≥ VDD – 0.2V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
10/06/02
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet IS61LF51218.PDF ] | |
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