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IS61LF51218 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS61LF51218
部品説明 (IS61LF25632 / IS61LF25636 / IS61LF51218) 256Kx32 Synchronous Flow-through Static RAM
メーカ ISSI
ロゴ ISSI ロゴ 



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IS61LF51218 Datasheet, IS61LF51218 PDF,ピン配置, 機能
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IS61LF25632T/D/J
ISSIIS61LF25636T/D/J IS61LF51218T/D/J
®
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
OCTOBER 2002
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global
Write
• Clock controlled, registered address, data
and control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Power Supply
+ 3.3V VDD
+ 3.3V or 2.5V VDDQ (I/0)
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• J version (PBGA Package with JTAG)
• D version (two chip selects)
• JTAG Boundary Scan for PBGA.
DESCRIPTION
The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are
high-speed, low-power synchronous static RAMs designed to
provide a burstable, high-performance and memories for
commucation and networking applications. The IS61LF25632
is organized as 262,144 words by 32 bits and the IS61LF25636
is organized as 262,144 words by 36 bits. The IS61LF51218 is
organized as 524,288 words by 18 bits. Fabricated with ISSI's
advanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers that are controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. Byte
write operation is performed by using byte write enable
(BWE).input combined with one or more individual byte write
signals (BWx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear
burst is achieved when this pin is tied LOW. Interleave burst is
achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
6.5 7.5
6.5 7.5
7.5 8.5
133 117
Units
ns
ns
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
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