No Preview Available !
( DataSheet : www.DataSheet4U.com )
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS FLOW-THROUGH
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Burst sequence control using MODE input
• Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VF: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball
PBGA and 165-pin PBGA packages.
• Lead-free available
FAST ACCESS TIME
Clock Access Time
The ISSI IS61LF/VF25672A, IS61LF/VF51236A and
IS61LF/VF102418A are high-speed, low-power synchro-
nous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LF/VF25672A is organized as
262,144 words by 72 bits. The IS61LF/VF51236A is orga-
nized as 524,288 words by 36 bits. The IS61LF/VF102418A
is organized as 1,048,576 words by 18 bits. Fabricated
with ISSI's advanced CMOS technology, the device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic cir-
cuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
No Preview Available !
(IS61xFxxxxxA) Synchronous Flow-through Static RAM
www.DataSheet.jp | 2020 | メール | 最新 | Sitemap