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IS64VF25618A の電気的特性と機能

IS64VF25618AのメーカーはISSIです、この部品の機能は「(IS6xxFxxxxxA) Synchronous Flow-through Static RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS64VF25618A
部品説明 (IS6xxFxxxxxA) Synchronous Flow-through Static RAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS64VF25618A Datasheet, IS64VF25618A PDF,ピン配置, 機能
( DataSheet : www.DataSheet4U.com )
IS61(64)LF12832A IS64VF12832A
IS61(64)LF12836A IS61(64)VF12836A
IS61(64)LF25618A IS61(64)VF25618A
ISSI®
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
PRELIMINARY INFORMATION
AUGUST 2005
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VF: VDD 2.5V -5% +10%, VDDQ 2.5V -5% +10%
• JEDEC 100-Pin TQFP, 119-pin PBGA, and
165-pin PBGA packages
• Automotive temperature available
• Lead-free available
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
DESCRIPTION
The ISSI IS61(64)LF12832A, IS64VF12832A,
IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are
high-speed, low-power synchronous static RAMs designed
to provide burstable, high-performance memory for commu-
nication and networking applications. The
IS61(64)LF12832A is organized as 131,072 words by 32
bits. The IS61(64)LF/VF12836A is organized as 131,072
words by 36 bits. The IS61(64)LF/VF25618A is organized
as 262,144 words by 18 bits. Fabricated with ISSI's
advanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All syn-
chronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
-6.5 -7.5
6.5 7.5
7.5 8.5
133 117
Units
ns
ns
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
08/11/05
www.DataSheet4U.com
1

1 Page





IS64VF25618A pdf, ピン配列
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
ISSI®
165-PIN BGA
165-Ball, 13x15 mm BGA
119-PIN BGA
119-Ball, 14x22 mm BGA
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
08/11/05
3


3Pages


IS64VF25618A 電子部品, 半導体
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
ISSI®
165 PBGA PACKAGE PIN CONFIGURATION
128K X 36 (TOP VIEW)
1
A NC
B NC
2
A
A
3 4 5 6 7 8 9 10
CE
BWc
BWb CE2
BWE ADSC ADV
A
CE2
BWd
BWa CLK
GW
OE
ADSP A
11
NC
NC
C DQPc NC
VDDQ
Vss
Vss
Vss
Vss
Vss
VDDQ
NC
DQPb
D DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
E DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
F DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
G DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
H NC NC NC VDD Vss Vss Vss VDD NC NC ZZ
J DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
K DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
L DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
M DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
N DQPd NC
VDDQ
Vss
NC
NC
NC
Vss
VDDQ
NC
DQPa
P NC NC A A NC A1* NC A A A NC
R MODE NC
A
A
NC A0* NC A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
A0, A1
ADV
ADSP
ADSC
GW
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
CLK
CE, CE2, CE2
BWx (x=a,b,c,d)
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
NC
DQx
DQPx
VDD
VDDQ
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
08/11/05

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS64VF25618A

(IS6xxFxxxxxA) Synchronous Flow-through Static RAM

ISSI
ISSI
IS64VF25618EC

SYNCHRONOUS FLOW-THROUGH SRAM

ISSI
ISSI


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