PDF IS61LF51236A Data sheet ( Hoja de datos )

Número de pieza	IS61LF51236A
Descripción	(IS61xFxxxxxA) Synchronous Flow-through Static RAM
Fabricantes	ISSI
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( DataSheet : www.DataSheet4U.com ) IS61LF25672A IS61VF25672A IS61LF51236A IS61VF51236A IS61LF102418A IS61VF102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM ISSI® AUGUST 2005 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expan- sion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VF: VDD 2.5V + 5%, VDDQ 2.5V + 5% • JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball PBGA and 165-pin PBGA packages. • Lead-free available FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency DESCRIPTION The ISSI IS61LF/VF25672A, IS61LF/VF51236A and IS61LF/VF102418A are high-speed, low-power synchro- nous static RAMs designed to provide burstable, high- performance memory for communication and networking applications. The IS61LF/VF25672A is organized as 262,144 words by 72 bits. The IS61LF/VF51236A is orga- nized as 524,288 words by 36 bits. The IS61LF/VF102418A is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device inte- grates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic cir- cuit. All synchronous inputs pass through registers con- trolled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address ad- vance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. -6.5 -7.5 6.5 7.5 7.5 8.5 133 117 Units ns ns MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 08/26/05 www.DataSheet4U.com 1 1 page IS61LF25672A IS61LF51236A IS61LF102418A IS61VF25672A IS61VF51236A IS61VF102418A ISSI® 119 BGA PACKAGE PIN CONFIGURATION-512K X 36 (TOP VIEW) 1 2 3 4 5 67 A VDDQ B NC A A A ADSP A A ADSC A A VDDQ A NC C NC A A VDD A A NC D DQc DQPc Vss E DQc DQc Vss F VDDQ G DQc DQc DQc Vss BWc NC CE OE ADV Vss Vss Vss BWb DQPb DQb DQb DQb DQb DQb VDDQ DQb H DQc DQc Vss GW Vss DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd L DQd M VDDQ DQd DQd DQd Vss BWd Vss CLK NC BWE Vss BWa Vss DQa DQa DQa DQa DQa VDDQ N DQd DQd Vss A1* Vss DQa DQa P DQd DQPd Vss A0* Vss DQPa DQa R NC A MODE VDD NC A NC T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol Pin Name A Address Inputs A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance. Address Status Processor ADSC GW Address Status Controller Global Write Enable CLK CE Synchronous Clock Synchronous Chip Select BWx (x=a-d) Synchronous Byte Write Controls BWE Byte Write Enable Symbol OE ZZ MODE TCK, TDO TMS, TDI NC DQa-DQd DQPa-Pd VDD VDDQ Vss Pin Name Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply Output Power Supply Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 08/26/05 5 5 Page IS61LF25672A IS61LF51236A IS61LF102418A IS61VF25672A IS61VF51236A IS61VF102418A ISSI® TRUTH TABLE(1-8) (3CE option) OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselect Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None X X X H X X X X X X High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 08/26/05 11 11 Page

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