C8051F321 Datasheet PDF - Silicon Laboratories
| Part Number | C8051F321 | |
| Description | (C8051F320 / C8051F321) Full Speed USB / 16k ISP FLASH MCU Family | |
| Manufacturers | Silicon Laboratories | |
| Logo |  |
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( DataSheet : www.DataSheet4U.com )
C8051F320/1
Full Speed USB, 16k ISP FLASH MCU Family
ANALOG PERIPHERALS
- 10-Bit ADC
• Up to 200 ksps
• Up to 17 or 13 External Single-Ended or Differential
Inputs
• VREF from External Pin, Internal Reference, or VDD
• Built-in Temperature Sensor
• External Conversion Start Input
- Two Comparators
- Internal Voltage Reference
- POR/Brown-Out Detector
USB FUNCTION CONTROLLER
- USB Specification 2.0 Compliant
- Full Speed (12 Mbps) or Low Speed (1.5 Mbps)
Operation
- Integrated Clock Recovery; No External Crystal
Required for Full Speed or Low Speed
- Supports Eight Flexible Endpoints
- 1k Byte USB Buffer Memory
- Integrated Transceiver; No External Resistors Required
ON-CHIP DEBUG
- On-Chip Debug Circuitry Facilitates Full Speed,
Non-Intrusive In-System Debug (No Emulator
Required!)
- Provides Breakpoints, Single Stepping,
Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using
ICE-Chips, Target Pods, and Sockets
VOLTAGE REGULATOR INPUT: 4.0V TO 5.25V
HIGH SPEED 8051 µC Core
- Pipelined Instruction Architecture; Executes 70% of
Instructions in 1 or 2 System Clocks
- Up to 25 MIPS Throughput with 25 MHz Clock
- Expanded Interrupt Handler
MEMORY
- 2304 Bytes Internal RAM (1k + 256 + 1k USB FIFO)
- 16k Bytes FLASH; In-system programmable in 512-byte
Sectors
DIGITAL PERIPHERALS
- 25/21 Port I/O; All 5 V tolerant with High Sink Current
- Hardware Enhanced SPI™, Enhanced UART, and
SMBus™ Serial Ports
- Four General Purpose 16-Bit Counter/Timers
- 16-Bit Programmable Counter Array (PCA) with Five
Capture/Compare Modules
- Real Time Clock Mode using External Clock Source and
PCA or Timer
CLOCK SOURCES
- Internal Oscillator: 0.25% Accuracy with Clock
Recovery enabled. Supports all USB and UART Modes
- External Oscillator: Crystal, RC, C, or Clock (1 or 2 Pin
Modes)
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Strategies
PACKAGES
- 32-pin LQFP (C8051F320)
- 28-pin MLP (C8051F321)
TEMPERATURE RANGE: -40°C TO +85°C
ANALOG
PERIPHERALS
A 10-bit +
M
U
X
200ksps
ADC
-
+
-
TEMP
SENSOR
VREF
VREG
DIGITAL I/O
UART
SPI
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
Port 1
Port 2
Port 3
PRECISION INTERNAL
OSCILLATOR
USB Controller /
Transceiver
HIGH-SPEED CONTROLLER CORE
16KB
ISP FLASH
16
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
2304 B
SRAM
POR WDT
Preliminary Rev. 1.1 12/03
Copyright © 2003 by Silicon Laboratories
C8051F320/1-DS11
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
www.DataSheet4U.com
www.DataSheet4U.com
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C8051F320/1
14.2. Port I/O Initialization.....................................................................................................131
14.3.General Purpose Port I/O...............................................................................................134
15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ....................................................143
15.1.Endpoint Addressing .....................................................................................................144
15.2. USB Transceiver ...........................................................................................................144
15.3. USB Register Access.....................................................................................................146
15.4.USB Clock Configuration .............................................................................................150
15.5. FIFO Management.........................................................................................................151
15.5.1. FIFO Split Mode ..................................................................................................151
15.5.2. FIFO Double Buffering .......................................................................................151
15.5.3. FIFO Access ........................................................................................................152
15.6. Function Addressing......................................................................................................153
15.7. Function Configuration and Control .............................................................................154
15.8. Interrupts .......................................................................................................................157
15.9.The Serial Interface Engine ...........................................................................................161
15.10.Endpoint0 .....................................................................................................................161
15.10.1.Endpoint0 SETUP Transactions .........................................................................162
15.10.2.Endpoint0 IN Transactions .................................................................................162
15.10.3.Endpoint0 OUT Transactions .............................................................................163
15.11.Configuring Endpoints1-3 ...........................................................................................166
15.12.Controlling Endpoints1-3 IN .......................................................................................166
15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode ...........................................................166
15.12.2.Endpoints1-3 IN Isochronous Mode...................................................................167
15.13.Controlling Endpoints1-3 OUT ...................................................................................170
15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode .......................................................170
15.13.2.Endpoints1-3 OUT Isochronous Mode...............................................................170
16. SMBUS..................................................................................................................................175
16.1. Supporting Documents ..................................................................................................176
16.2. SMBus Configuration....................................................................................................176
16.3. SMBus Operation ..........................................................................................................177
16.3.1. Arbitration............................................................................................................177
16.3.2. Clock Low Extension...........................................................................................178
16.3.3. SCL Low Timeout ...............................................................................................178
16.3.4. SCL High (SMBus Free) Timeout.......................................................................178
16.4. Using the SMBus...........................................................................................................179
16.4.1. SMBus Configuration Register............................................................................180
16.4.2. SMB0CN Control Register ..................................................................................183
16.4.3. Data Register........................................................................................................186
16.5. SMBus Transfer Modes.................................................................................................187
16.5.1. Master Transmitter Mode ....................................................................................187
16.5.2. Master Receiver Mode.........................................................................................188
16.5.3. Slave Receiver Mode ...........................................................................................189
16.5.4. Slave Transmitter Mode.......................................................................................190
16.6. SMBus Status Decoding................................................................................................191
17. UART0 ..................................................................................................................................193
Rev. 1.1
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ C8051F321.PDF Datasheet ] | |
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