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16C550 の電気的特性と機能

16C550のメーカーはETCです、この部品の機能は「TL16C550」です。


製品の詳細 ( Datasheet PDF )

部品番号 16C550
部品説明 TL16C550
メーカ ETC
ロゴ ETC ロゴ 




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16C550 Datasheet, 16C550 PDF,ピン配置, 機能
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
D Capable of Running With All Existing
TL16C450 Software
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
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D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 – 1) and Generates an Internal 16×
Clock
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D Independent Receiver Clock Input
D Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
D Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)
D False-Start Bit Detection
D Complete Status Reporting Capabilities
D 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
Functionally identical to the TL16C450 on power up (character mode), the TL16C550A can be placed in an
alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.
The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (216 – 1) and producing a 16 × clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
The TL16C550A can also be reset to the TL16C450 mode under software control.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1

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16C550 pdf, ピン配列
block diagram
Internal
Data Bus
8 –1
D7 – D0
Line
Control
Register
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
S
e
l
e
c
t
Receiver
Buffer
Register
Receiver
FIFO
Receiver
Buffer
Register
10
SIN
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28
A0
27
A1
26
A2
12
CS0
13
CS1
14
CS2
25
ADS
35
MR
21
RD1
22
RD2
18
WR1
WR2 19
DDIS 23
TXRDY 24
XIN 16
XOUT 17
RXRDY 29
Select
and
Control
Logic
Line
Control
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
40
VCC
20
VSS
Power
Supply
Interrupt
Enable
Register
Interrupt
I/O
Register
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the N package.
Baud
Generator
Transmitter
FIFO
S
e
l
e
c
t
Interrupt
Control
Logic
Receiver
Timing and
Control
9
RCLK
15
BAUDOUT
Line
Control
Register
Line
Control
Register
Modem
Control
Logic
11
SOUT
32
RTS
36
CTS
33 DTR
37
DSR
38
DCD
39
RI
34
OUT1
31
OUT2
30
INTRPT
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3


3Pages


16C550 電子部品, 半導体
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
absolute maximum ratings over free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
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recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA
MIN
4.75
2
– 0.5
0
NOM
5
MAX
5.25
VCC
0.8
70
UNIT
V
V
V
°C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VOH‡
VOL‡
Ilkg
PARAMETER
High-level output voltage
Low-level output voltage
Input leakage current
IOZ High-impedance output current
TEST CONDITIONS
IOH = – 1 mA
IOL = 1.6 mA
VCC = 5.25 V,
VI = 0 to 5.25 V,
VSS = 0,
All other terminals floating
VCC = 5.25 V,
VSS = 0
VO = 0 to 5.25 V,
Chip selected in write mode or chip deselected
MIN TYP†
2.4
MAX
0.4
UNIT
V
V
± 10 µA
± 20 µA
ICC Supply current
VCC = 5.25 V,
TA = 25°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kbit/s
CXIN
CXOUT
Ci
Co
Clock input capacitance
Clock output capacitance
Input capacitance
Output capacitance
VCC = 0,
VSS = 0,
All other terminals grounded,
f = 1 MHz,
TA = 25°C
† All typical values are at VCC = 5 V, TA = 25°C.
These parameters apply for all outputs except XOUT.
10 mA
15 20 pF
20 30 pF
6 10 pF
10 20 pF
6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

6 Page



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共有リンク

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