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PDF MRFIC1859 Data sheet ( Hoja de datos )
| Número de pieza | MRFIC1859 | |
| Descripción | Dual Band / GSM 3.6V Integrated Power Amplifier | |
| Fabricantes | Motorola Semiconductors | |
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Order this document by MRFIC1859/D
Dual-Band/GSM 3.6 V
Integrated Power Amplifier
MRFIC1859
The MRFIC1859 is a dual–band, single supply RF Power Amplifier for
GSM900/DCS1800 hand held radios. The on–chip spur free voltage
generator reduces the number of external components by eliminating the
need for a negative voltage supply. The device output power can be
controlled open loop without the use of directional coupler and detection
diode. The MRFIC1859 is General Packet Radio Service (GPRS)
compatible. The device is packaged in a TQFP–32EP with exposed
backside pad allowing excellent electrical and thermal performance through
a solderable contact.
• Single Positive Supply Solution
• Input/Output External Matching
• High Power and Efficiency
• Typical 3.6 V Characteristics:
Pout = 36.2 dBm, PAE = 53% for GSM
Pout = 34 dBm, PAE = 43% for DCS
• Crosstalk Harmonic Leakage of –27 dBm Typical (GSM)
DUAL–BAND
GSM 3.6 V IPA
SEMICONDUCTOR
TECHNICAL DATA
32 1
(Scale 2:1)
PLASTIC PACKAGE
CASE 873E
(TQFP–32EP)
ORDERING INFORMATION
Device
Operating
Temperature Range Package
MRFIC1859R2 TC = –35 to 100°C TQFP–32EP
Simplified Block Diagram
D1G D2B B2B
B1G
D2G
B23G
InG OutG
Negative and Positive
Voltage Generator
VSS
VP
VSC
InD OutD
B1D
D1D D1B
B23D
G2D
D2D
This device contains 21 active transistors.
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
© Motorola, Inc. 2000
Rev 4
1
1 page  
MRFIC1859
Pin No.
22,23
Symbol
D2D
I/O
I
PIN FUNCTION DESCRIPTION (continued)
Description
Functionality
DCS 2nd stage
drain
Power supply for DCS driver stage, and inter–staging matching. These pins form
the required inductor for a proper match.
24 B23D
25,26,27, OutD
28,29
30 B2B
31 D2B
32 VSS
Exposed
Pad
Gnd
I DCS Bias for 2nd Same as Pin 1 for DCS amplifier.
and 3rd stage
O DCS RF Output RF output and power supply for output DCS stage. Supply voltage is provided
through those five pins. An external matching network is required to provide
optimum load impedance.
I Buffer 2nd state Like Pins 1, 15, and 18, this is a bias pin. Pin 30 is used to bias 2nd stage of buffer
Bias amplifier.
I Buffer 2nd stage Drain supply and matching of buffer amplifier to maximize VSS and VP voltages.
Drain
O Negative Voltage A buffer amplifier is designed to produce the required negative voltage, based on
RF signal amplification with a two stages wide band amplifier and rectification of the
resulting signal. An external zener diode is used to regulate this voltage and
provide to the gates a stabilized biasing voltage. VSS is also used to switch off the
unused amplifier. Refer to Bias Pins 1, 18 and 15, 24.
I
Main Gnd
The bottom pad of the TQFP–32EP package is used for electrical/RF grounding
and thermal dissipation. The PCB pattern where it fits has to be tailored for good
ground and thermal continuity (with many ground via holes).
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
5
5 Page 
MRFIC1859
APPLICATIONS INFORMATION
Design Philosophy
The MRFIC1859 is a dual–band single supply RF
integrated power amplifier designed for use in
GSM900/DCS1800 handheld radios under 3.6 V operation.
With matching circuit modifications, it is also applicable for
use in triple band GSM900/DCS1800/PCS1900 equipment.
Typical performances in GSM/DCS at 3.6 V are: GSM: 35.8
dBm with 53% PAE and, DCS: 34 dBm with 43% PAE.
It features a large band (900 to 1800 MHz) internal
Negative Voltage Generator based on RF rectification of the
input carrier after its amplification by two dedicated buffer
stages (See Simplified Block Diagram). This method
eliminates spurs found on the output signal when using dc/dc
converter type negative voltage generators, either on or off
chip. The buffer generates also a step–up positive voltage,
which can be used to drive a NMOS drain switch.
External Circuit Considerations
The MRFIC1859 can be tuned by changing the values
and/or positions of the appropriate external components (see
Figure 1: Application Schematic). While tuning the RF
line–up, it is recommended to apply external negative supply
in order to prevent any damage to the power amplifier stages.
Poor tuning on the input may not provide enough RF power to
operate the negative voltage generator properly.
Input matching is a shunt–C, series–L, low pass structure
for GSM and a shunt–L, series–L high pass structure for
DCS. It should be optimized at the rated input power (e.g. 3.0
dBm in GSM, 5.0 dBm in DCS). Since the input lines feed
both 1st stages and 1st stage buffers, input matching should
be iterated with buffer and Q1 drain matching. Note that dc
blocking capacitors are included on chip.
First stage buffer amplifier is tuned with a short 80 Ω
microstrip line which may be replaced by a chip inductor.
Second stage buffer amplifier is supplied and matched
through a discrete chip inductor. Those two elements are
tuned to get the maximum output from voltage generator. The
overall typical buffer current (DB1 + DB2) is about 60 mA in
GSM and 100 mA in DCS. However, the negative generator
needs a settling time of 1.0 µs (see burst mode paragraph).
During this transient period of time, both stages are biased to
IDSS, which is about 200 mA each.
The step–up positive voltage available at Pin 2, which is
approximately 10 V in each band, can be used to drive a
NMOS drain switch for best performances.
Q1 drains are supplied and matched through 80 Ω printed
microstrip lines that could be replaced by discrete chip
inductors as well. Their lengths (or equivalent inductor
values) are tuned by sliding the RF decoupling capacitors
along to get the maximum gain on the first stages.
Q2 drains are supplied through 60 Ω printed microstrip
lines that contribute also to the interstage matching in order
to optimum drive to the final stages.
The line length for Q2G and Q2D is small, so replacing it
with discrete inductors is not practical.
Q3 stages are fed via 50 Ω printed microstrip lines that
must handle the high supply current of that stages (2.0 Amp
peak) without significant voltage drop. This line can be buried
in an inner layer to save PCB space or be a discrete RF
choke.
Output matching is accomplished in both bands with two
stages low pass networks. Easy implementation is achieved
with shunt capacitors mounted along a 50 Ω microstrip
transmission line. Value and position are chosen to reach a
load line of 2.0 Ω while conjugating the device output
parasitics. The networks must also properly terminate the
second and third harmonic level. Use of high–Q capacitors
for the first output matching capacitor circuits is
recommended in order to get the best output power and
efficiency performances.
Note: the choice of output matching capacitor type and
supplier will affect H2 and H3 level and efficiency, because of
series resonant frequency.
Tuning Methodology
The following section gives the user some guidelines and
hints to tune and optimize the MRFIC1859 operation inside
their own radio PCB. First of all, one must keep in mind that
negative and positive voltage generation is based on RF
carrier rectification. This means that RF input signal must
always be present when running the part as a standalone
solution. Therefore, in order to ease the tuning phase, it is
recommended to apply the negative voltage externally in
order to avoid any damage to the large RF MESFET
transistors. This is particularly true if one uses the complete
application with MC33170 (product of On Semiconductor) as
control IC to do the optimization. In that case, both negative
and positive voltage should be provided externally.
The RF decoupling capacitors have been selected as 47
pF for GSM band (C17, C14, C22, C9. C1, and C8) and 22 pF
or 12 pF for DCS band (C10, C15, and C13). But those can
be optimized depending on their size and source, for
example 12 pF were used at some places for DCS to provide
better decoupling of the harmonics too, thus providing some
extra performance.
The recommended tuning procedure consists of several
steps that need to be performed in sequential order. Several
iterations can be performed if appropriate. Due to low
interaction between line–ups, each band can be tuned
independently.
• Optimize the buffer operation using D1B (T8 line) and D2B
matching (L3 inductor). Simultaneously, tune GSM or DCS
input matching using L1, C21 or L2, T10, respectively.
Check the margin on Pin to generate VSS and VP (those
voltages should still meet their specification with a 5.0 dB
reduction in Pin). A small shunt capacitor can be placed on
VP to maximize that voltage.
• Optimize RF line up linear gain using D1G, D2G matching
(T9 line) or D1D, D2D, G2D matching (T7 line, C8) for GSM
or DCS line–up, respectively. The goal is to maximize and
center small signal gain. Pin has to be reduced for this
exercise, hence the negative voltage needs to be applied
externally. A broad band measurement is helpful to
visualize the frequency response. Linear gain should peak
at around 40 dB for GSM and 32 dB for DCS. The input
matching has to be checked again and eventually refined
during this step.
• Optimize output matching using T4, C3, T1, C4 and T2 for
GSM or T6, C2, T5, C6, T3 for DCS, respectively. Those
elements set the Pout/PAE trade–off and harmonics
rejection performance.
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MRFIC1859.PDF ] | |
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