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DJLXT971A の電気的特性と機能

DJLXT971AのメーカーはIntelです、この部品の機能は「Dual Speed Fast Ethernet PHY Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 DJLXT971A
部品説明 Dual Speed Fast Ethernet PHY Transceiver
メーカ Intel
ロゴ Intel ロゴ 




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DJLXT971A Datasheet, DJLXT971A PDF,ピン配置, 機能
( DataSheet : www.DataSheet4U.com )
Intel® LXT971A
3.3V Dual-Speed Fast Ethernet PHY Transceiver
Datasheet
The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a
Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks.
This document also supports the LXT971 device.
The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
Combination 10BASE-T/100BASE-TX or 10/100 PCMCIA Cards
100BASE-FX Network Interface Cards
(NICs)
Cable Modems and Set-Top Boxes
Product Features
3.3V Operation.
Low power consumption (300 mW
typical).
Low-power “Sleep” mode.
10BASE-T and 100BASE-TX using a
single RJ-45 connection.
Supports auto-negotiation and parallel
detection.
MII interface with extended register
capability.
Robust baseline wander correction
performance.
100BASE-FX fiber-optic capable.
Standard CSMA/CD or full-duplex
operation.
Supports JTAG boundary scan.
Configurable via MDIO serial port or
hardware control pins.
Integrated, programmable LED drivers.
64-ball Plastic Ball Grid Array (PBGA).
— LXT971ABC - Commercial (0° to
70°C ambient).
— LXT971ABE - Extended (-40° to 85°C
ambient).
64-pin Low-profile Quad Flat Package
(LQFP).
— LXT971ALC - Commercial (0° to
70°C ambient).
— LXT971ALE - Extended (-40° to 85°C
ambient).
www.DataSheet4U.com
Order Number:A2u4g9wu4sw1t4w2-00.D0022ataSheet4U.com

1 Page





DJLXT971A pdf, ピン配列
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Contents
1.0 Pin Assignments ..............................................................................................................................12
2.0 Signal Descriptions ..........................................................................................................................16
3.0 Functional Description.....................................................................................................................21
3.1 Introduction .......................................................................................................................21
3.1.1 Comprehensive Functionality .............................................................................21
3.1.2 OSP™ Architecture ............................................................................................21
3.2 Network Media / Protocol Support....................................................................................22
3.2.1 10/100 Network Interface ...................................................................................22
3.2.1.1 Twisted-Pair Interface ..........................................................................22
3.2.1.2 Fiber Interface.......................................................................................22
3.2.1.3 Fault Detection and Reporting..............................................................23
3.2.2 MII Data Interface...............................................................................................23
3.2.2.1 Increased MII Drive Strength ...............................................................23
3.2.3 Configuration Management Interface .................................................................24
3.2.3.1 MDIO Management Interface ..............................................................24
3.2.3.2 Hardware Control Interface ..................................................................25
3.3 Operating Requirements....................................................................................................26
3.3.1 Power Requirements ...........................................................................................26
3.3.2 Clock Requirements............................................................................................26
3.3.2.1 External Crystal/Oscillator ...................................................................26
3.3.2.2 MDIO Clock .........................................................................................26
3.4 Initialization.......................................................................................................................26
3.4.1 MDIO Control Mode ..........................................................................................26
3.4.2 Hardware Control Mode .....................................................................................27
3.4.3 Reduced Power Modes........................................................................................28
3.4.3.1 Hardware Power Down ........................................................................28
3.4.3.2 Software Power Down..........................................................................29
3.4.3.3 Sleep Mode ...........................................................................................29
3.4.4 Reset....................................................................................................................29
3.4.5 Hardware Configuration Settings........................................................................30
3.5 Establishing Link...............................................................................................................31
3.5.1 Auto-Negotiation ................................................................................................31
3.5.1.1 Base Page Exchange .............................................................................31
3.5.1.2 Next Page Exchange .............................................................................31
3.5.1.3 Controlling Auto-Negotiation...............................................................31
3.5.2 Parallel Detection ................................................................................................31
3.6 MII Operation....................................................................................................................32
3.6.1 MII Clocks ..........................................................................................................32
3.6.2 Transmit Enable ..................................................................................................33
3.6.3 Receive Data Valid .............................................................................................33
3.6.4 Carrier Sense .......................................................................................................33
3.6.5 Error Signals .......................................................................................................33
3.6.6 Collision ..............................................................................................................33
3.6.7 Loopback.............................................................................................................34
3.6.7.1 Operational Loopback ..........................................................................35
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
3


3Pages


DJLXT971A 電子部品, 半導体
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Tables
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49
LQFP Numeric Pin List .................................................................................................... 12
LXT971A MII Signal Descriptions .................................................................................. 14
LXT971A Network Interface Signal Descriptions ........................................................... 15
LXT971A Miscellaneous Signal Descriptions ................................................................. 16
LXT971A Power Supply Signal Descriptions.................................................................. 17
LXT971A JTAG Test Signal Descriptions ...................................................................... 17
LXT971A LED Signal Descriptions ................................................................................ 17
Hardware Configuration Settings ..................................................................................... 26
Carrier Sense, Loopback, and Collision Conditions......................................................... 32
4B/5B Coding ................................................................................................................... 36
BSR Mode of Operation ................................................................................................... 43
Supported JTAG Instructions ........................................................................................... 43
Device ID Register ........................................................................................................... 43
Magnetics Requirements .................................................................................................. 44
I/O Pin Comparison of NIC and Switch RJ-45 Setups..................................................... 44
Absolute Maximum Ratings ............................................................................................. 49
Operating Conditions........................................................................................................ 49
Digital I/O Characteristics 1 ............................................................................................. 50
Digital I/O Characteristics - MII Pins............................................................................... 50
I/O Characteristics - REFCLK/XI and XO Pins............................................................... 50
I/O Characteristics - LED/CFG Pins ................................................................................ 50
100BASE-TX Transceiver Characteristics....................................................................... 51
100BASE-FX Transceiver Characteristics ....................................................................... 51
10BASE-T Transceiver Characteristics............................................................................ 51
10BASE-T Link Integrity Timing Characteristics ........................................................... 52
100BASE-TX Receive Timing Parameters - 4B Mode.................................................... 53
100BASE-TX Transmit Timing Parameters - 4B Mode .................................................. 54
100BASE-FX Receive Timing Parameters ...................................................................... 55
100BASE-FX Transmit Timing Parameters..................................................................... 56
10BASE-T Receive Timing Parameters........................................................................... 57
10BASE-T Transmit Timing Parameters ......................................................................... 58
10BASE-T Jabber and Unjabber Timing Parameters....................................................... 59
10BASE-T SQE Timing Parameters ................................................................................ 59
Auto Negotiation and Fast Link Pulse Timing Parameters .............................................. 60
MDIO Timing Parameters ................................................................................................ 61
Power-Up Timing Parameters .......................................................................................... 62
RESET Pulse Width and Recovery Timing Parameters.................................................. 62
Register Set....................................................................................................................... 63
Register Bit Map............................................................................................................... 64
Control Register (Address 0) ............................................................................................ 66
MII Status Register #1 (Address 1) .................................................................................. 67
PHY Identification Register 1 (Address 2)....................................................................... 68
PHY Identification Register 2 (Address 3)....................................................................... 68
Auto Negotiation Advertisement Register (Address 4).................................................... 69
Auto Negotiation Link Partner Base Page Ability Register (Address 5) ......................... 70
Auto Negotiation Expansion (Address 6)......................................................................... 71
Auto Negotiation Next Page Transmit Register (Address 7) ........................................... 71
Auto Negotiation Link Partner Next Page Receive Register (Address 8)........................ 72
Configuration Register (Address 16, Hex 10) .................................................................. 73
6 Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002

6 Page



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部品番号部品説明メーカ
DJLXT971A

Dual Speed Fast Ethernet PHY Transceiver

Intel
Intel
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Dual Speed Fast Ethernet PHY Transceiver

Intel
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