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GVT71256C36 の電気的特性と機能

GVT71256C36のメーカーはCypress Semiconductorです、この部品の機能は「(GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GVT71256C36
部品説明 (GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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GVT71256C36 Datasheet, GVT71256C36 PDF,ピン配置, 機能
( DataSheet : www.DataSheet4U.com )
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K x 36/512K x 18 Pipelined SRAM
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and
150 MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for performance (two cycle chip deselect, depth
expansion without wait state)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The CY7C1366A/GVT71256C36 and CY7C1367A/
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x
18 SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW). However, the CE2 Chip Enable input is only available for
the TA(GVTI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide, as controlled by the write control inputs.
Individual byte write allows an individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc.
BWd controls DQd. BWa, BWb, BWc, and BWd can be active
only with BWE being LOW. GW being LOW causes all bytes
to be written. The x18 version only has 18 data inputs/outputs
(DQa and DQb) along with BWa and BWb (no BWc, BWd,
DQc, and DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The CY7C1366A/GVT71256C36 and CY7C1367A/
GVT71512C18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Selection Guide
7C1366A-225/
71256C36-4.4
7C1367A-225/
71512C18-4.4
Maximum Access Time (ns)
2.5
Maximum Operating Current (mA)
Commercial
570
Maximum CMOS Standby Current (mA)
10
7C1366A-200/
71256C36-5
7C1367A-200/
71512C18-5
3.0
510
10
7C1366A-166/
71256C36-6
7C1367A-166/
71512C18-6
3.5
425
10
7C1366A-150/
71256C36-6.7
7C1367A-150/
71512C18-6.7
3.5
380
10
www.DataSheet4U.com
wwwC.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 12, 2001

1 Page





GVT71256C36 pdf, ピン配列
Pin Configurations
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
100-Pin TQFP
Top View
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 CY7C1366A/GVT71256C36 66
16 65
17 (256K X 36) 64
18
19
T Package Version
63
62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 CY7C1367A/GVT71512C18 66
16
(512K x 18)
65
17 64
18
T Package Version
63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
A
NC
NC
VCCQ
VSS
NC
DPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15
16
CY7C1366A/GVT71256C36
66
65
17 (256K X 36) 64
18
19
TA Package Version
63
62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 CY7C1367A/GVT71512C18 66
16
(512K x 18)
65
17 64
18
TA Package Version
63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
A
NC
NC
VCCQ
VSS
NC
DPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
3


3Pages


GVT71256C36 電子部品, 半導体
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K X 36 Pin Descriptions (continued)
X36 PBGA Pins X36 QFP Pins Name
(a) 6P, 7P, 7N, 6N, (a) 51, 52, 53, 56,
6M, 6L, 7L, 6K, 7K, 57, 58, 59, 62, 63
(b) 7H, 6H, 7G, 6G, (b) 68, 69, 72, 73,
6F, 6E, 7E, 7D, 6D, 74, 75, 78, 79, 80
(c) 2D, 1D, 1E, 2E, (c) 1, 2, 3, 6, 7, 8,
2F, 1G, 2G, 1H, 2H,
9, 12, 13
(d) 1K, 2K, 1L, 2L, (d) 18, 19, 22, 23,
2M, 1N, 2N, 1P, 2P 24, 25, 28, 29, 30
DQa
DQb
DQc
DQd
2U 38 TMS
3U 39 TDI
4U 43 TCK
for B and T
version
5U 42 TDO
for B and T
version
4C, 2J, 4J, 6J, 4R 15, 41,65, 91
3D, 5D, 3E, 5E, 3F,
5F, 3H, 5H, 3K, 5K,
3M, 5M, 3N, 5N,
3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67,
71, 76, 90
VCC
VSS
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54, VCCQ
7J, 1M, 7M, 1U, 7U 61, 70, 77
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
14, 16, 66
38, 39, 42 for TA
Version
NC
Type
Input/
Output
Input
Output
Supply
Ground
I/O Supply
-
Description
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
TA package version.
IEEE 1149.1 test output. LVTTL-level output. Not available for
TA package version.
Core power Supply: +3.3V 5% and +10%
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
512K X 18 Pin Descriptions
X18 PBGA Pins
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T,
5T, 6T
5L
3G
X18 QFP Pins
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46,
45, 44, 49, 50
92 (T Version)
43 (TA Version)
93
94
4M 87
4H 88
4K 89
4E 98
Name
A0
A1
A
BWa
BWb
BWE
GW
CLK
CE
Type
Description
Input-
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
Input-
Write Enable: This active LOW input gates byte write opera-
Synchronous tions and must meet the set up and hold times around the rising
edge of CLK.
Input-
Global Write: This active LOW input allows a full 18-bit WRITE
Synchronous to occur independent of the BWE and WEn lines and must
meet the set up and hold times around the rising edge of CLK.
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around
the clocks rising edge.
Input-
Chip Enable: This active LOW input is used to enable the de-
Synchronous vice and to gate ADSP.
6

6 Page



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部品番号部品説明メーカ
GVT71256C36

(GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM

Cypress Semiconductor
Cypress Semiconductor


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