PDF MT48G16M16LF Data sheet ( Hoja de datos )

Número de pieza	MT48G16M16LF
Descripción	(MT48xx16M16LF) 4M x 16 x 4 Banks
Fabricantes	Micron Technology
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MOBILE SDRAM PRELIMINARY‡ 256Mb: x16 MOBILE SDRAM MT48LC16M16LF, MT48G16M16LF, MT48V16M16LF 4 MEG X 16 X 4 BANKS Features • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes • Self Refresh Mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Low voltage power supply • Temperature Compensated Self Refresh (TCSR) Option • VDD/VDDQ Marking 3.3V/3.3V 3.0V/3.0V LC G 2.5V/2.5V-1.8V • Configurations 16 Meg x 16 (4 Meg x 16 x 4 banks) V 16M16 • Plastic Packages - OCPL 54-pin TSOP (400 mil)1 54-pin TSOP (400 mil) Lead-Free1 54-ball VFBGA (8mm x 14mm)2 54-ball VFBGA (8mm x 14mm) Lead-Free2 54-ball VFBGA (11mm x 8mm)2 54-ball VFBGA (11mm x 8mm) Lead-Free2 • Timing (Cycle Time) TG P FG BG F8 B8 7.5ns @ CL = 3 (133MHz) 8.0ns @ CL = 3 (125 MHz) -75 -8 9.6ns @ CL = 3 (104 MHz) • Self Refresh Standard -10 None • Operating Temperature Commercial (0oC to + 70oC) Extended (-25oC to + 75oC) Industrial (-40oC to + 85oC) None XT IT NOTE: 1. Contact Factory for availability. 2. Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site, www.micron.com/decoder. Figure 1: Ball Assignment (Top View) 54-Ball VFBGA 123456789 A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS\ RAS\ WE\ G A12 A11 A9 BA0 BA1 CS\ H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 16 Meg x 16 4 Meg x 16 x 4 banks 8K 8K (A0-A12) 4 (BA0, BA1) 512 (A0-A8) Table 1: Key Timing Parameters SPEED CLOCK GRADE FREQUENCY ACCESS TIME1 CL=1 CL=2 CL=3 -75 133 MHz - - 5.4ns -8 125 MHz - - 7ns -10 104 MHz - 8ns 7ns -75 104 MHz - 6ns - -8 104 MHz - 8ns - -10 83 MHz - 8ns - -8 50 MHz 19ns - - NOTE: 1. *CL = CAS (READ) latency SETUP TIME 1.5ns 2.5ns 2.5ns 1.5ns 2.5ns 2.5ns 2.5ns HOLD TIME 0.8ns 1.0ns 1.0ns 1.0ns 1.0ns 1.0ns 1.0ns www.DataSheet4U.com 09005aef80737ef7 256Mbx16_1.fm - Rev. E 4/04 EN 1 ©2002 Micron Technology, Inc. All rights reserved. ww‡PwR.ODDatUaCSThSeAetN4DU.ScPoEmCIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. www.DataSheet4U.com 1 page PRELIMINARY 256Mb: x16 MOBILE SDRAM Figure 2: Pin Assignment (Top View) 54-Pin TSOP x16 VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 VDDQ DQ5 DQ6 VssQ DQ7 VDD DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 x16 54 Vss 53 DQ15 52 VssQ 51 DQ14 50 DQ13 49 VDDQ 48 DQ12 47 DQ11 46 VssQ 45 DQ10 44 DQ9 43 VDDQ 42 DQ8 41 Vss 40 NC 39 DQMH 38 CLK 37 CKE 36 A12 35 A11 34 A9 33 A8 32 A7 31 A6 30 A5 29 A4 28 Vss 09005aef80737ef7 256Mbx16_2.fm - Rev. E 4/04 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved. 5 Page CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all rele- vant access times are met, if a READ command is regis- tered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Figure 4 indi- cates the operating frequencies at which each CAS latency setting can be used. Figure 6: CAS Latency T0 T1 T2 T3 CLK T4 T5 COMMAND READ NOP NOP ADDRESS BANK, COL n NOP READ NOP X = 0 cycles BANK, COL b DQ DOUT n CAS Latency = 1 DOUT n+1 DOUT n+2 DOUT n+3 DOUT b T0 T1 T2 T3 CLK T4 T5 T6 COMMAND READ NOP NOP ADDRESS BANK, COL n NOP READ NOP X = 1 cycle BANK, COL b NOP DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CAS Latency = 2 T0 T1 T2 T3 CLK T4 T5 T6 T7 COMMAND READ NOP NOP ADDRESS BANK, COL n DQ CAS Latency = 3 NOP READ NOP NOP NOP BANK, COL b X = 2 cycles DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b TRANSITIONING DATA DON’T CARE NOTE: Each READ command may be to either bank. DQM is LOW. BL=4 PRELIMINARY 256Mb: x16 MOBILE SDRAM Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0- M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (non- burst) accesses. Table 4: CAS Latency ALLOWABLE OPERATING FREQUENCY (MHZ) CAS CAS CAS SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3 - 75 - 104 133 - 8 50 104 125 - 10 40 83 104 09005aef80737ef7 256Mbx16_2.fm - Rev. E 4/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved. 11 Page

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