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IS62WV5128BLL の電気的特性と機能

IS62WV5128BLLのメーカーはIntegrated Silicon Solutionです、この部品の機能は「(IS62WV51218A(B)LL) 512K x 16 Low Voltage / Ultra Low Power CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS62WV5128BLL
部品説明 (IS62WV51218A(B)LL) 512K x 16 Low Voltage / Ultra Low Power CMOS SRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS62WV5128BLL Datasheet, IS62WV5128BLL PDF,ピン配置, 機能
IS62WV5128ALL
IS62WV5128BLL
ISSI®
512K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
APRIL 2003
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation
36 mW (typical) operating
9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
1.65V – 2.2V VDD (IS62WV5128ALL)
2.5V – 3.6V VDD (IS62WV5128BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
DESCRIPTION
The ISSI IS62WV5128ALL / IS62WV5128BLL are high-
speed, 4M bit static RAMs organized as 512K words by 8
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV5128ALL and IS62WV5128BLL are packaged
in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin
sTSOP (TYPE I), and 32-pin TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 8
MEMORY ARRAY
VDD
GND
I/O0-I/O7
I/O
DATA
CIRCUIT
COLUMN I/O
CS1
OE
WE
CONTROL
CIRCUIT
www.DataSheet4U.com
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
www0.4D/30/03ataSheet4U.com
1

1 Page





IS62WV5128BLL pdf, ピン配列
IS62WV5128ALL, IS62WV5128BLL
OPERATING RANGE (VDD)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
IS62WV5128ALL
1.65V - 2.2V
1.65V - 2.2V
ISSI ®
IS62WV5128BLL
2.5V - 3.6V
2.5V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VTERM
Terminal Voltage with Respect to GND
–0.2 to VDD+0.3
V
VDD VDD Related to GND
–0.2 to VDD+0.3
V
TSTG
Storage Temperature
–65 to +150
°C
PT Power Dissipation
1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VDD
VOH
Output HIGH Voltage
IOH = -0.1 mA
IOH = -1 mA
1.65-2.2V
2.5-3.6V
VOL
Output LOW Voltage
IOL = 0.1 mA
IOL = 2.1 mA
1.65-2.2V
2.5-3.6V
VIH Input HIGH Voltage
1.65-2.2V
2.5-3.6V
VIL(1)
Input LOW Voltage
1.65-2.2V
2.5-3.6V
ILI Input Leakage
GND VIN VDD
ILO Output Leakage
GND VOUT VDD, Outputs Disabled
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
Min.
1.4
2.2
1.4
2.2
–0.2
–0.2
–1
–1
Max.
0.2
0.4
VDD + 0.2
VDD + 0.3
0.4
0.6
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/30/03
3


3Pages


IS62WV5128BLL 電子部品, 半導体
IS62WV5128ALL, IS62WV5128BLL
ISSI ®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
55 ns
Min. Max.
70 ns
Min. Max.
Unit
tRC Read Cycle Time
55 —
70 —
ns
tAA Address Access Time
— 55
— 70
ns
tOHA Output Hold Time
10 —
10 —
ns
tACS1
CS1 Access Time
— 55
— 70
ns
tDOE OE Access Time
— 25
— 35
ns
tHZOE(2)
OE to High-Z Output
— 20
— 25
ns
tLZOE(2)
OE to Low-Z Output
5—
5—
ns
tHZCS1
CS1 to High-Z Output
0 20
0 25
ns
tLZCS1
CS1 to Low-Z Output
10 —
10 —
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, WE = VIH)
ADDRESS
DOUT
tRC
PREVIOUS DATA VALID
tOHA
tAA
tOHA
DATA VALID
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/30/03

6 Page



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部品番号部品説明メーカ
IS62WV5128BLL

(IS62WV51218A(B)LL) 512K x 16 Low Voltage / Ultra Low Power CMOS SRAM

Integrated Silicon Solution
Integrated Silicon Solution


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