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CA3282 の電気的特性と機能

CA3282のメーカーはIntersil Corporationです、この部品の機能は「Octal Low Side Power Driver with Serial Bus Control」です。


製品の詳細 ( Datasheet PDF )

部品番号 CA3282
部品説明 Octal Low Side Power Driver with Serial Bus Control
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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CA3282 Datasheet, CA3282 PDF,ピン配置, 機能
TM CA3282
June 1998
Octal Low Side Power Driver
with Serial Bus Control
Features
Description
• Output Current Drive Capability
The CA3282 is a logic controlled, eight channel octal power
- All Outputs ON, Equal . . . . . . . . . . . . . . 0.625A Each
- Per Output Individually . . . . . . . . . . . . . . . . . 1A Each
- Maximum Total of Outputs ON . . . . . . . . . . . . . . . . 5A
driven. The serial peripheral interface (SPI) utilized by the
CA3282 is a serial synchronous bus compatible with Intersil
CDP68HC05, or equivalent, microcomputers. As shown in
the Block Diagram for the CA3282 each of the open drain
• High Voltage Power BiMOS Outputs
- 8 Open Drain NDMOS Drivers
m- Individual Output Latch
- Over-Current Limit Protection . . . . . . . . . . . . . 1.05A
o- Over-Voltage Clamp Protection . . . . . . . . . . . . . . 30V
.c• High Speed CMOS Logic Control
- Low Quiescent IDD Current . . . . . . . . . . . . . . . . . 5mA
U- SPI Bus Controlled Interface
- Individual Fault Unlatch and Feedback
t4- Common Reset Line
• Operating Temperature Range . . . . . . . -40oC to 125oC
eeApplications
h• Automotive and Industrial Systems
• Solenoids, Relays and Lamp Drivers
S• Logic and µP Controlled Drivers
ta• Robotic Controls
NDMOS output drivers has individual protection for over-
voltage and over-current. Each output channel has separate
output latch control with fault unlatch and diagnostic feed-
back. Under normal ON conditions, each output driver is in a
low, saturation state. Comparators in the diagnostic circuitry
monitor the output drivers to determine if an out of saturation
condition exists. If a comparator senses a fault, the respec-
tive output driver is unlatched. In addition, over current pro-
tection is provided with current limiting in each output,
independent of the diagnostic feedback loop.
The CA3282 is fabricated in a Power BiMOS IC process, and is
intended for use in automotive and other applications having a
wide range of temperature and electrical stress conditions. It is
particularly suited for driving lamps, relays, and solenoids in
applications where low operating power, high breakdown volt-
age, and high output current at high temperatures is required.
The CA3282 is supplied in 15 lead plastic SIP package with
lead forms for either vertical or surface mount.
Ordering Information
PART
NUMBER
TEMP.
RANGE(oC)
PACKAGE AND
LEAD FORM
PKG
NO.
a CA3282AS1
.D CA3282AS2
-40 to 125
-40 to 125
15 Ld Plastic SIP
Staggered Vertical
15 Ld Plastic SIP
Surface Mount
Z15.05A
Z15.05B
wPinout
ww U.comNOTE:
t4HEAT SINK TAB
INTERNALLY
eCONNECTED TO
.DataSheGROUND (VSS)
CA3282 (SIP)
TOP VIEW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Block Diagram
OUTPUT #0
(1 OF 8)
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
RESET
VDD
MISO
VSS
MOSI
SCK
CE
OUTPUT 0
OUTPUT 1
OUTPUT 2
OUTPUT 3
MOSI
SCK
MISO
CE
RESET
SHIFT
REGISTER
OUTPUT
LATCH
CURRENT
LIMIT
CONTROL
LOGIC
DIAGNOSTIC
CIRCUITRY
TO DRIVERS
1 THRU 7
wwCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
w1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 2767.6
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1

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CA3282 pdf, ピン配列
CA3282
Electrical Specifications VDD = 5V, TA = -40oC to 125oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
Output Three State Leakage
Current
IOL VDD = 5.25V, 0 < VO < VDD,
CE Pin Held High
-10 -
Output Capacitance
COUT 0 < VO < VDD, CE Pin Held High
--
MAX
+10
UNITS
µA
20 pF
Serial Peripheral Interface Timing (See Figure 1B)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Frequency
fOPER
D.C. Note 4 3.0
MHz
Enable Lead Time
(2) tLEAD
- <100 200 ns
Enable Lag Time
(3) tLAG
- <100 200 ns
Clock HIGH Time
(4) twSCK
H
- 50 100 ns
Clock LOW Time
(5) twSCK
L
- 50 100 ns
Data Setup Time
(6) tSU
- 20 50 ns
Data Hold Time
(7) tH
- 20 50 ns
Enable Time
(8) tEN
- 50 100 ns
Disable Time
(9) tDIS
-
150 300
ns
Data Valid Time
(10) tV
- 75 150 ns
Output Data Hold Time
(11) tHO
0 50 - ns
Rise Time (MISO Output)
(12) trSO VDD = 20% to 70%, CL = 200pF
- 35 100 ns
Rise Time SPI Inputs (SCK, MOSI, CE)
(12) trSI VDD = 20% to 70%, CL = 200pF
-
- 50 ns
Fall Time (MISO Output)
(13) tfSO VDD = 70% to 20%, CL = 200pF
- 45 100 ns
Fall Time SPI Inputs (SCK, MOSI, CE)
(13) tfSI VDD = 70% to 20%, CL = 200pF
-
- 50 ns
NOTES:
3. Refer to Figure 4A for IOUT current vs VSAT voltage. Typical rDS(ON) values are given for -40oC, 25oC, 105oC and 125oC temperatures.
4. The Maximum Operating Frequency is typically greater than 10MHz but it is application limited primarily by external SPI input rise/fall
times and MISO output loading.
Timing Diagrams
CE
SCK
(CPOL = 0, CPHA = 1)
MSB 6 5 4 3
2 1 LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
3


3Pages


CA3282 電子部品, 半導体
CA3282
Output Drivers
The output drivers provide and active low output of 500mA
nominal with current limiting set to 1.05A to allow for high
inrush currents. In addition, each output is provided with a
voltage clamp circuit to limit inductive transients. Each out-
put driver is also monitored by a comparator for an out of
saturation condition. If the output voltage of an ON output
pin exceeds the saturation voltage limit, a fault condition is
assumed and the latch driving this output is reset, turning
the output off. The output comparators, which also provide
diagnostic feedback data to the shift register, contain an
internal pull-down current which will cause the cell to indi-
cate a low output voltage if the output is programmed OFF
and the output pin is open circuited.
shows a zero, then the probable cause is an open circuit
resulting in a floating output.
1.5
rDS(ON) = 0.48
rDS(ON) = 0.54
rDS(ON) = 0.67
1.0 rDS(ON) = 0.78
-40×oC
25C
105×oC
125×oC
0.5
CE High to Low Transition
When CE is low the three state MISO pin is enabled. On
the falling edge of CE, diagnostic data from the output volt-
age comparators will be latched into the shift register. If an
output is high, a logic one will be loaded into that bit in the
shift register. If the output is low, a logic zero will be loaded.
During the time that CE is low, data bytes controlling the
output drivers are shifted in at the MOSI pin most signifi-
cant bit (MSB) first. A logic zero on this pin will program the
corresponding output to be ON, and a logic one will turn it
OFF.
0
0.2 0.4 0.6 0.8
SATURATION VOLTAGE (VSAT)
FIGURE 3A. CA3282 TYPICAL OUTPUT DRIVER rDS(ON)
CHARACTERISTICS OF CURRENT OUT vs
SATURATION VOLTAGE, VSAT FOR A -40oC TO
125oC JUNCTION TEMPERATURE
CE Low to High Transition
When the last data bit has been shifted into the CA3282,
the CE pin should be pulled high. At the rising edge of CE,
shift register data is latched into the output latch and the
outputs are activated with the new data. An internal 150µs
delay timer will start at this rising edge to compensate for
high inrush currents in lamps and inductive loads. During
this period, the outputs will be protected only by the analog
current limiting circuits since resetting of the output latches
by fault conditions will be inhibited during this time. This
allows the device to handle inrush currents immediately
after turn on. When the 150µs delay has elapsed, the out-
put voltages are sensed by the comparators and any out of
saturation outputs are latched off. The serial clock input pin
(SCK) should be low during CE transitions to avoid false
clocking of the shift register. The SCK input is gated by CE
so that the SCK input is ignored when CE is high.
Detecting Fault Conditions
Fault conditions may be checked as follows. Clock in a new
control byte and wait approximately 150µs to allow the out-
puts to settle. Clock in the same control byte and note the
diagnostic data output at the MISO pin. The diagnostic bits
should be identical to the data clocked in. Any differences
will indicate a fault in the corresponding outputs. For exam-
ple, if an output was programmed ON by clocking in a zero,
and the corresponding diagnostic bit for that output is a
one, indicating the driver output is still high, then a short cir-
cuit or overload condition may have caused the output to
unlatch. Alternatively, if the output was programmed OFF
by clocking in one, and the diagnostic bit for that output
TYP CURRENT LIMITING
1.5
1.0
0.5
-40oC
25oC
105oC
125oC
0
0
0.5 1.0
SATURATION VOLTAGE (VSAT)
1.5
FIGURE 3B. CA3282 TYPICAL OUTPUT DRIVER rDS(ON)
CHARACTERISTICS OF CURRENT OUT vs
1S2A5ToUCRJAUTNIOCNTIVOONLTTAEMGEP,EVRSAATTUFROER A -40oC TO
Dissipation In Multiple Outputs
The CA3282 Octal Power Driver has multiple MOS Output
Drivers and requires special consideration with regard to
maximum current and dissipation ratings. While each output
has a maximum current specification consistent with the
device structure, all such devices on the chip can not be
simultaneously rated to the same high level of peak current.
The total combined current and the dissipation on the chip
must be adjusted for maximum allowable ratings, given
simultaneous multiple output conditions.
6

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共有リンク

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