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PDF ISP1501 Data sheet ( Hoja de datos )
| Número de pieza | ISP1501 | |
| Descripción | Hi-speed Universal Serial Bus Peripheral Transceiver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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ISP1501
Hi-Speed Universal Serial Bus peripheral transceiver
Rev. 02 — 21 November 2002
Product data
1. General description
The ISP1501 is a full-function transceiver designed to provide a Hi-Speed Universal
Serial Bus (USB) analog front-end to Application-Specific Integrated Circuits (ASICs)
and Field Programmable Gate Arrays (FPGAs) with a built-in USB Serial Interface
Engine (SIE). A Hi-Speed USB transceiver is integrated to implement USB
connectivity for high-speed peripherals. In addition, an Original USB transceiver
provides backward compatibility with full-speed USB systems. A minimum number of
external components is needed.
2. Features
s Complies with Universal Serial Bus Specification Rev. 2.0
s Legacy compliant Original USB full-speed transceiver interface
s Bus-powered capability with suspend mode
s Integrated parallel-to-serial converter (transmit) and serial-to-parallel converter
(receive) for Hi-Speed USB data
s Hi-Speed USB data recovery upon receiving
s Hi-Speed USB data synchronization upon transmitting
s Integrated bit stuffing and de-stuffing for Hi-Speed USB data
s Non-Return-to-Zero Inverted (NRZI) encoding and decoding for Hi-Speed
USB data
s Integrated Phase Locked Loop (PLL) oscillator using 12 MHz crystal
s Internal power-on reset
s Separate 3.3 V supplies for analog transceiver and digital I/Os minimizes
crosstalk
s 3.3 V or 5 V tolerant digital input interface
s 16-bit bi-directional data bus allows FPGA verification, greatly reducing ASIC
implementation risk
s Full industrial operating temperature range from −40 to +85 °C
s 6 kV in-circuit ESD protection; compliant with IEC 61000-4-2 (level 3)
s Available in LQFP48 package.
1 page  
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
9397 750 10025
Product data
Table 2: Pin description…continued
Symbol[1]
Pin Type Description
DP 7 AI/O USB D+ connection (analog) with integrated 45 Ω series
resistor
VCCA2
RPU
8-
9 AI
analog supply voltage 2 (3.3 V)
connection for external pull-up resistor (1.5 kΩ ± 5%) on
USB D+; switched on via internal switch during the FS and
HS chirp states
AGND2
10 -
analog ground 2 supply
MODE0
11 I
operating state and interface selection input 0; see Table 3
MODE1
12 I
operating state and interface selection input 1; see Table 3
CLKOUT48
13 O
48 MHz clock output; clock is always running when input
SUSPEND is logic 0; see Section 17 on application of this
clock
RREF
14 AI
connection for external reference resistor (12 kΩ ± 1%) to
analog ground supply
CLKOUT30
15 O
clock output for Hi-Speed USB digital interface (30 MHz);
clock is always running when input SUSPEND is logic 0
VCCA3
XTAL2
16 -
17 AO
analog supply voltage 3 (3.3 V)
crystal oscillator output (12 MHz)
XTAL1
18 AI crystal oscillator input (12 MHz)
AGND3
19 -
analog ground 3 supply
DDIR
20 I
selects direction of 16-bit data bus DATA[15:0]
DATA0
21 I/O data bit 0; bi-directional, slew rate controlled output (5 ns)
DATA1
22 I/O data bit 1; bi-directional, slew rate controlled output (5 ns)
DATA2
23 I/O data bit 2; bi-directional, slew rate controlled output (5 ns)
DATA3
24 I/O data bit 3; bi-directional, slew rate controlled output (5 ns)
DATA4
25 I/O data bit 4; bi-directional, slew rate controlled output (5 ns)
DATA5
26 I/O data bit 5; bi-directional, slew rate controlled output (5 ns)
DATA6
27 I/O data bit 6; bi-directional, slew rate controlled output (5 ns)
DATA7
28 I/O data bit 7; bi-directional, slew rate controlled output (5 ns)
VCCD1
DGND1
29 -
30 -
digital supply voltage 1 (3.3 V)
digital ground 1 supply
DATA8
31 I/O data bit 8; bi-directional, slew rate controlled output (5 ns)
DATA9
32 I/O data bit 9; bi-directional, slew rate controlled output (5 ns)
DATA10
33 I/O data bit 10; bi-directional, slew rate controlled output (5 ns)
DATA11
34 I/O data bit 11; bi-directional, slew rate controlled output (5 ns)
DATA12
35 I/O data bit 12; bi-directional, slew rate controlled output (5 ns)
DATA13
36 I/O data bit 13; bi-directional, slew rate controlled output (5 ns)
DATA14
37 I/O data bit 14; bi-directional, slew rate controlled output (5 ns)
DATA15
38 I/O data bit 15; bi-directional, slew rate controlled output (5 ns)
RX_LAST_BYTE 39 O logic 0 — DATA[7:0] = valid data, DATA[15:8] = valid data
logic 1 — DATA[7:0] = valid data, DATA[15:8] = bit stuff
error byte
VCCD2
40 -
digital supply voltage 2 (3.3 V)
Rev. 02 — 21 November 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5 of 40
5 Page 
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
8.2.2 Full-speed (FS) state
In the full-speed (FS) state (MODE[1:0] = 01), an external pull-up resistor of
1.5 kΩ ± 5% is required on the DP line. This is implemented via the RPU resistor. The
RPU resistor is internally connected to the DP line. The FS transceiver is enabled,
and the legacy (Original USB) SIE interface is active (see Figure 4).
ISP1501
3.3 V
9 RPU
1.5 kΩ
± 5%
Fig 4. Full-speed state.
45 Ω
45 Ω
FS driver
7 DP
6 DM
004aaa052
8.2.3 High-speed (HS) state
In the high-speed (HS) state, internal 45 Ω resistors on the DP and DM lines are
connected to the ground. The pull-up resistor is disconnected. The HS transceiver is
enabled, and the parallel interface and the HS-handshake signals are used (see
Figure 5).
ISP1501
3.3 V
9 RPU
1.5 kΩ
± 5%
HS current
driver
7 DP
6 DM
45 Ω 45 Ω
9397 750 10025
Product data
Fig 5. High-speed state.
004aaa041
8.2.4 High-speed (HS) chirp state
In the high-speed (HS) chirp state, 45 Ω terminations are disabled from the
DP and DM lines. The pull-up resistor is connected on the DP line. The
HS transceiver is enabled, and the parallel interface and HS handshake signals are in
use (see Figure 6).
Rev. 02 — 21 November 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
11 of 40
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