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FW21555 の電気的特性と機能

FW21555のメーカーはIntelです、この部品の機能は「PCI-to-PCI Bridge」です。


製品の詳細 ( Datasheet PDF )

部品番号 FW21555
部品説明 PCI-to-PCI Bridge
メーカ Intel
ロゴ Intel ロゴ 




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FW21555 Datasheet, FW21555 PDF,ピン配置, 機能
taSh2Be1er5itd45Ug5.ecNomon-Transparent PCI-to-PCIDatasheet
ww.Da Product Featuress Full compliance with the PCI local Bus
w Specification, Revision 2.2, plus:
m—PCI Power Management support
— Vital Product Data (VPD) support
o—CompactPCI Distributed Hot-Swap
.csupport
s 3.3-V operation with 5.0-V tolerant I/O
s Selectable asynchronous or synchronous
Uprimary and secondary interface clocks
t4s Concurrent primary and secondary bus
operation
s Fully compliant with the Advanced
eConfiguration Power Interface (ACPI)
specification
es Fully compliant with the PCI Bus Power
Management specification
hs Queuing of multiple transactions in either
direction
Ss 256 bytes of posted write (data and
taaddress) buffering in each direction
s 256 bytes of read data buffering in each
direction
as Four delayed transaction entries in each
direction
.Ds Two dedicated I2O delayed transaction
entries
s Two sets of standard PCI Configuration
wregisters corresponding to the primary and
secondary interface; each set is accessible
from either the primary or secondary
winterface
ms Direct offset address translation for
w odownstream memory and I/O transactions
.cs Hardware enable for secondary bus central
functions
t4Us IEEE Standard 1149.1 boundary-scan
JTAG interface
s Four primary interface base address
configuration registers for downstream
forwarding, with size and prefetchability
programmable for all four address ranges
s Three secondary interface address
configuration registers specifying local
address ranges for upstream forwarding,
with size and prefetchability programmable
for all three address ranges
s Inverse decoding above the 4 GB address
boundary for upstream DACs
s Ability to generate Type 0 and Type 1
configuration commands on the primary or
secondary interface via configuration or I/O
CSR accesses
s Ability to generate I/O commands on the
primary or secondary interface via I/O CSR
accesses
s I2O message unit
s Doorbell registers for software generation
of primary and secondary bus interrupts, 16
bits per interface
s Eight Dwords of scratchpad registers
s Generic own bit (can memory-map)
semaphore
s Parallel flash ROM interface with primary
bus expansion ROM base address register
s Serial ROM interface
s Secondary bus arbiter support for up to
nine external devices at 33 MHz and up to
four external devices at 66 MHz (in
addition to the 21555)
s Secondary bus clock output for
synchronous operation
s Four 32-bit base address configuration
registers mapping the 21555 control and
status registers (CSRs)
s Available in 33 MHz and 66 MHz versions
heeNotice: This document contains preliminary information on new products in production. The
Sspecifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
www.DataOrder Number: 278320-002

1 Page





FW21555 pdf, ピン配列
Contents
Contents
1.0 Introduction.................................................................................................................................... 5
1.1 Comparing 21555 and Standard PCI-to-PCI Bridge ............................................................. 5
1.2 Architectural Overview.......................................................................................................... 8
2.0 Pin Assignment ...........................................................................................................................10
2.1 Pin Location List (Alphanumeric) ........................................................................................12
2.2 Pin Signal List (Alphanumeric)............................................................................................17
3.0 Electrical Specifications .............................................................................................................22
3.1 PCI Electrical Specification Conformance ..........................................................................22
3.2 Absolute Maximum Ratings ................................................................................................22
3.3 DC Specifications ...............................................................................................................23
3.4 AC Timing Specifications .................................................................................................... 23
3.4.1 Clock Timing Specifications ...................................................................................23
3.4.2 PCI Signal Timing Specifications ...........................................................................25
3.4.3 Reset Timing Specifications ..................................................................................26
3.4.4 Serial ROM Timing Specifications .........................................................................27
3.4.5 Parallel ROM Timing Specifications.......................................................................27
3.4.6 JTAG Timing Specifications...................................................................................28
4.0 Mechanical Specifications ..........................................................................................................29
Figures
1 21555 Intelligent Controller Application ........................................................................................ 6
2 21555 Microarchitecture ............................................................................................................... 9
3 21555 PBGA Cavity Down View.................................................................................................11
4 PCI Clock Signal AC Parameter Measurements ........................................................................25
5 PCI Signal Timing Measurement Conditions ..............................................................................25
6 304 PBGA (Four-Layer) Package...............................................................................................29
Tables
1 21555 and PPB Feature Comparison...........................................................................................7
2 Signal Type Abbreviations ..........................................................................................................10
3 21555 Pin Location List (Alphanumeric) .....................................................................................12
4 21555 Pin Signal List (Alphanumeric).........................................................................................17
5 Absolute Maximum Ratings ........................................................................................................22
6 Functional Operating Range.......................................................................................................22
7 DC Parameters ...........................................................................................................................23
8 33 MHz PCI Clock Signal AC Parameters..................................................................................24
9 66 MHz PCI Clock Signal AC Parameters..................................................................................24
10 33 MHz PCI Signal Timing Specifications ..................................................................................26
11 66 MHz PCI Signal Timing Specifications ..................................................................................26
12 Reset Timing Specifications .......................................................................................................26
13 Serial ROM Timing Specifications ..............................................................................................27
14 Parallel ROM Timing Specifications ...........................................................................................27
15 JTAG Timing Specifications........................................................................................................28
Datasheet
iii


3Pages


FW21555 電子部品, 半導体
Non-Transparent PPB
It was a primary goal of the PCI-to-PCI bridge architecture that a PPB be transparent to devices
and device drivers. For example, no changes are needed to a device driver when a PCI peripheral is
located behind a PPB. Once configured during system initialization, a PPB operates without the aid
of a device driver. A PPB does not require a device driver of its own since it does not have any
resources that must be managed by software during run-time. This requirement for transparency
forced the usage of a flat addressing model across PCI-to-PCI bridges. This means that a given
physical address exists at only one location in the PCI bus hierarchy and that this location may be
accessed by any device attached at any point in the PCI bus hierarchy. As a consequence, it is not
possible for a PPB to isolate devices or address ranges from access by devices on the opposite
interface of a PPB. The PPB architecture assumes that the resources of any device in a PCI system
are configured and managed by the host processor.
However, there are applications where the transparency of a PCI-to-PCI bridge is not desired. For
example, Figure 1 shows a hypothetical PCI add-in card used for an intelligent subsystem
application.
Figure 1. 21555 Intelligent Controller Application
Intelligent Subsystem
DRAM/
ROM
PCI
Device
PCI
Device
PCI
Device
Memory
Local
CPU
CPU-
PCI
Bridge
PCI Bus
Intel®
21555
Device
PCI Bus
Host
Core
Logic
Host
CPU
A8826-01
Assume that the local processor on the add-in card is used to manage the resources of the devices
attached to the add-in cards local PCI bus. Assume also that it is desirable to restrict access to
these same resources from other PCI bus masters in the system and from the host processor. In
addition, there is a need to resolve address conflicts that may exist between the host system and the
local processor. The non transparency of the 21555 is perfectly suited to this kind of configuration,
where a transparent PCI-to-PCI bridge is problematic.
Because the 21555 is not transparent, the device driver for the add-in card must be aware of the
presence of the 21555 and manage its resources appropriately. The 21555 allows the entire
subsystem to appear as a single virtual device to the host. This enables configuration software to
identify the appropriate driver for the subsystem.
With a transparent PCI-to-PCI bridge, a driver does not need to know about the presence of the
bridge and manage its resources. The subsystem appears to the host system as individual PCI
devices on a secondary PCI bus, not as a single virtual device.
Table 1 shows a comparison between a 21555 and a standard transparent PCI-to-PCI bridge.
6 Datasheet

6 Page



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部品番号部品説明メーカ
FW21555

PCI-to-PCI Bridge

Intel
Intel


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