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PDF NT256D64S88ABG Data sheet ( Hoja de datos )
| Número de pieza | NT256D64S88ABG | |
| Descripción | 256MB DIMM | |
| Fabricantes | Nanya Technology | |
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NT256D64S88ABG
256MB : 32M x 64
omPC2700 Unbuffered DIMM
U.c184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR333 32Mx8 SDRAM
heet4Features
S• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
ta• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
a• Performance:
.DSpeed Sort
PC2700
-6
Unit
wDIMM CAS Latency
2.5 2
wf CK Clock Frequency
166 133 MHz
w t CK Clock Cycle
6 7.5 ns
f DQ DQ Burst Frequency
333
266 MHz
• Intended for 100 MHz and 133 MHz applications
m• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
o• SDRAMs have 4 internal banks for concurrent operation
.c• Module has one physical bank
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock
transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto-Refresh (CBR) and Self-Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
t4UDescription
NT256D64S88ABG is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
eorganized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR
eSDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 333MHz. The DIMM is intended for use
hin applications operating from 133 MHz to 166 MHz clock speeds with data rates of 266 to 333 MHz. Clock enable CKE0 controls all
Sdevices on the DIMM.
taPrior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
aThese DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
.DThe DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
wAll NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
wwOrdering Information
Part Number
NT256D64S88ABG-6
REV 1.1
08/2002
Speed
166MHz (6ns @ CL = 2.5)
133MHz (7.5ns @ CL= 2)
.comPC2700
Organization
32Mx64
Leads
Gold
Power
2.5V
w.DataSheet4U1
© NANYA TECHNOLOGY CORP.
wwNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1 page  
NT256D64S88ABG
256MB : 32M x 64
PC2700 Unbuffered DIMM
Serial Presence Detect -- Part 1 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
Byte
Description
SPD Entry Value
DDR333
Serial PD Data Entry (Hexadecimal) Note
DDR333
-6 -6
0
Number of Serial PD Bytes Written during
Production
128
80
1 Total Number of Bytes in Serial PD device
256
08
2 Fundamental Memory Type
SDRAM DDR
07
3 Number of Row Addresses on Assembly
13
0D
4 Number of Column Addresses on Assembly
10
0A
5 Number of DIMM Bank
1 01
6 Data Width of Assembly
X64 40
7 Data Width of Assembly (cont’) X64 00
8 Voltage Interface Level of this Assembly
SSTL 2.5V
04
9 DDR SDRAM Device Cycle Time at CL=2.5
6ns
60
10
DDR SDRAM Device Access Time from Clock
at CL=2.5
0.7ns
70
11 DIMM Configuration Type
Non-Parity
00
12 Refresh Rate/Type
SR/1x(7.8µs)
82
13 Primary DDR SDRAM Width
X8 08
14 Error Checking DDR SDRAM Device Width
N/A
00
15
DDR SDRAM Device Attr: Min CLK Delay,
Random Col Access
1 Clock
01
16
DDR SDRAM Device Attributes:
Burst Length Supported
2,4,8
0E
17
DDR SDRAM Device Attributes: Number of
Device Banks
4
04
18
DDR SDRAM Device Attributes: CAS Latencies
Supported
2/2.5
0C
19 DDR SDRAM Device Attributes: CS Latency
0
01
20 DDR SDRAM Device Attributes: WE Latency
1
02
21 DDR SDRAM Device Attributes:
Differential Clock
20
22 DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23 Minimum Clock Cycle at CL=2
7.5ns
75
24
Maximum Data Access Time from Clock at
CL=2
0.7ns
70
25 Minimum Clock Cycle Time at CL=1
N/A
00
26
Maximum Data Access Time from Clock at
CL=1
N/A
00
27 Minimum Row Precharge Time (tRP)
18ns
48
28
Minimum Row Active to Row Active delay
(tRRD)
12ns
30
29 Minimum RAS to CAS delay (tRCD)
18ns
48
30 Minimum RAS Pulse Width (tRAS)
42ns
2A
31 Module Bank Density
256MB
40
32
Address and Command Setup Time Before
Clock
0.75ns
75
33 Address and Command Hold Time After Clock
0.75ns
75
34 Data Input Setup Time Before Clock
0.45ns
45
35 Data Input Hold Time After Clock
0.45ns
45
36-61 Reserved
Undefined
00
62 SPD Revision
Initial
00
63 Checksum Data
0A
REV 1.1
08/2002
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
5 Page 
NT256D64S88ABG
256MB : 32M x 64
PC2700 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
tAC
tDQSCK
tCH
tCL
tCK
tCK
tDH
tDS
tDIPW
tHZ
tLZ
tDQSQ
tDQSQA
tHP
tQHS
tQH
tDQSS
tDQSL,H
tDSS
tDSH
tMRD
tWPRES
tWPST
tWPRE
tIH
tIS
tIH
tIS
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock cycle time
CL=2.5
CL=2
DQ and DM input hold time
DQ and DM input setup time
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
DQS-DQ skew (DQS & associated DQ signals)
DQS-DQ skew (DQS & all DQ signals)
Minimum half clk period for any given cycle;
defined by clk high (tCH ) or clk low (tCL ) time
Data Hold Skew Factor
Data output hold time from DQS
Write command to 1st DQS latching transition
DQS input low (high) pulse width (write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input hold time (fast slew
rate)
Address and control input setup time (fast slew
rate)
Address and control input hold time (slow slew
rate)
Address and control input setup time (slow slew
rate)
-6
Min.
-0.7
-0.7
0.45
0.45
6
7.5
0.45
0.45
1.75
-0.7
-0.7
min
(tCH, tCL)
0.55
tHP - tQHS
0.75
0.35
0.2
0.2
12
0
0.40
0.25
0.75
Max.
+0.7
+0.7
0.55
0.55
12
12
+0.7
+0.7
0.4
0.4
1.25
0.60
0.75
0.8
0.8
Unit Notes
ns 1-4
ns 1-4
tCK 1-4
tCK 1-4
ns 1-4
ns 1-4
ns 1-4, 15, 16
ns 1-4, 15, 16
ns 1-4
ns 1-5
ns 1-5
ns 1-4
ns 1-4
tCK 1-4
Ns
tCK 1-4
tCK 1-4
tCK 1-4
tCK 1-4
tCK 1-4
ns 1-4
ns 1-4, 7
tCK 1-4, 6
tCK 1-4
ns
2-4, 9, 11,
12
ns
2-4, 9, 11,
12
ns
2-4, 10-12,
14
ns
2-4, 10-12,
14
REV 1.1
08/2002
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
11 Page | ||
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| PDF Descargar | [ Datasheet NT256D64S88ABG.PDF ] | |
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