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NT256D64S8HA0G-6 の電気的特性と機能

NT256D64S8HA0G-6のメーカーはNanya Technologyです、この部品の機能は「256MB DIMM」です。


製品の詳細 ( Datasheet PDF )

部品番号 NT256D64S8HA0G-6
部品説明 256MB DIMM
メーカ Nanya Technology
ロゴ Nanya Technology ロゴ 




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NT256D64S8HA0G-6 Datasheet, NT256D64S8HA0G-6 PDF,ピン配置, 機能
NT256D64S8HA0G-6
256MB : 32M x 64
omPC2700 Unbuffered DIMM
U.c184pin Two Bank Unbuffered DDR SDRAM MODULE Based on DDR333 16Mx8 SDRAM
eet4Features
h• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
S• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
ta• Performance :
a PC2700
.DSpeed Sort
-6 Unit
wDIMM CAS Latency
2.5 2
wf CK Clock Frequency
166 133 MHz
w t CK Clock Cycle
6 7.5 ns
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
f DQ DQ Burst Frequency
333
266 MHz
• Intended for 166 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
m• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
o• Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
.c• Module has two physical banks
• Differential clock inputs
• Data is read or written on both clock edges
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 12/10/2 Addressing (row/column/bank)
• 15.6 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
t4UDescription
NT256D64S8HA0G-6 is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
eorganized as a dual-bank high-speed memory array. The 32Mx64 module is a two-bank DIMM that uses sixteen 16Mx8 DDR
eSDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 333MHz. The DIMM is intended for use
hin applications operating from 133 MHz to 166 MHz clock speeds with data rates of 266 to 333 MHz. Clock enable CKE0 and / or CKE1
Scontrols all devices on the DIMM.
taPrior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
aThese DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
.DThe DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
wAll NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
wwOrdering Information
Part Number
NT256D64S8HA0G-6
Preliminary, 11/2001
Speed
166MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
.comPC2700
Organization
32Mx64
Leads
Gold
Power
2.5V
w.DataSheet4U1
w © NANYA TECHNOLOGY CORP.
wNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

1 Page





NT256D64S8HA0G-6 pdf, ピン配列
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Input/Output Functional Description
Symbol
CK0 , CK1, CK2
CK0 , CK1 , CK2
CKE0, CKE1
S0 , S1
RAS , CAS , WE
VREF
VDDQ
BA0, BA1
A0 - A9
A10/AP
A11
DQ0 - DQ63,
DQS0 - DQS7
DQS9 - DQS16
VDD , VSS
SA0 – SA2
SDA
SCL
VDDSPD
Type
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
Polarity
Function
The positive line of the differential pair of system clock inputs which drives the input to the
Positive
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
Edge
edge of their associated clocks.
Negative The negative line of the differential pair of system clock inputs which drives the input to the
Edge on-DIMM PLL.
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Active
Low
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
Active When sampled at the positive rising edge of the clock, RAS , CAS , WE define the
Low operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
- Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
- invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
- Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Active Data strobes: Output with read data, input with write data. Edge aligned with read data,
High centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
- Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
- This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
-
connected from the SCL bus time to V DD to act as a pullup.
Serial EEPROM positive power supply.
Preliminary, 11/2001
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.


3Pages


NT256D64S8HA0G-6 電子部品, 半導体
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
DC Electrical Characteristics and Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
VDD
VDDQ
VSS , VSSQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
Parameter
Supply Voltage
I/O Supply Voltage
Supply Voltage, I/O Supply Voltage
/O Reference Voltage
I/O Termination Voltage (System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level, CK and CK Inputs
Input Differential Voltage, CK and CK Inputs
Min Max
2.3 2.7
2.3 2.7
00
0.49 x VDDQ 0.51 x VDDQ
VREF – 0.04 VREF + 0.04
VREF + 0.15 VDDQ + 0.3
-0.3 VREF- 0.15
-0.3 VDDQ + 0.3
0.30
V DDQ + 0.6
Units
V
V
V
V
V
V
V
V
V
Notes
1
1
1,2
1,3
1
1
1
1,4
Input Leakage Current
II
Any input 0V VIN VDD; (All other pins not under test = 0V)
-5
5 µA 1
Output Leakage Current
IOZ
(DQs are disabled; 0V Vout VDDQ
-5 5 µA 1
Output High Current
IOH
(VOUT = VDDQ -0.373V, min VREF , min VTT )
-16.8
- mA 1
Output Low Current
IOL
(VOUT = 0.373, max VREF , max VTT )
16.8 - mA 1
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF ,
and must track variations in the DC level of VREF .
4. VID is the magnitude of the difference between the input level on CK and the input level on CK .
Preliminary, 11/2001
6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

6 Page



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部品番号部品説明メーカ
NT256D64S8HA0G-6

256MB DIMM

Nanya Technology
Nanya Technology


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