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NT256S64V8HC0G の電気的特性と機能

NT256S64V8HC0GのメーカーはNanya Technologyです、この部品の機能は「256MB SDRAM Module」です。


製品の詳細 ( Datasheet PDF )

部品番号 NT256S64V8HC0G
部品説明 256MB SDRAM Module
メーカ Nanya Technology
ロゴ Nanya Technology ロゴ 




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NT256S64V8HC0G Datasheet, NT256S64V8HC0G PDF,ピン配置, 機能
NT256S64V8HC0G
256MB : 32M x 64
mUnbuffered SDRAM Module
.co32Mx64 bit Two Bank Unbuffered SDRAM Module
based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
et4UFeatures
hel 168-Pin Unbuffered 8-Byte Dual In-Line Memory Module
Sl Intended for PC133 applications
ta- Clock Frequency: 133MHz
a- Clock Cycle: 7.5ns
.D- Clock Assess Time: 5.4ns
l Inputs and outputs are LVTTL (3.3V) compatible
wl Single 3.3V ± 0.3V Power Supply
wl Single Pulsed RAS interface
wl SDRAMs have 4 internal banks
l
l
l
l
Automatic and controlled Precharge commands
Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
Suspend Mode and Power Down Mode
4096 Refresh cycles distributed across 64ms
l Module has 2 physical bank
l Fully Synchronous to positive Clock Edge
ml Data Mask for Byte Read/Write control
l Auto Refresh (CBR) and Self Refresh
l Gold contacts
l SDRAMs in TSOP Type II Package
l Serial Presence Detect with Write Protect
.coDescription
NT256S64V8HC0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which is organized as 32Mx64
Uhigh-speed memory arrays and is configured as two 16M x 64 physical bank. The DIMM uses sixteen 16Mx8 SDRAMs in 400mil TSOP II
pack-ages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that
t4supports the JEDEC 1N rule while allowing very low burst power.
eAll control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations
eof RAS , CAS , WE , S0 - S3 , DQMB, and CKE0 – CKE1 signals. A command decoder initiates the necessary timings for each operation. A
h14-bit address bus accepts address information in a row / column multiplexing arrangement.
SPrior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by
address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using
tathe two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.
.DaOrdering Information
Part Number
wwwNT256S64V8HC0G-7K
MHz.
143MHz
133MHz
133MHz
Speed
CL
3
2
3
t RCD
3
2
3
t RP
3
2
3
Organization
Leads
Power
NT256S64V8HC0G-75B
NT256S64V8HC0G-8B
* CL = CAS Latency
Preliminary 10 / 2001
100MHz
125MHz
100MHz
222
om3 3 3
.c2 2 2
32Mx64
Gold
3.3V
w.DataSheet4U1
w © NANYA TECHNOLOGY CORP.
wNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

1 Page





NT256S64V8HC0G pdf, ピン配列
NT256S64V8HC0G
256MB : 32M x 64
Unbuffered SDRAM Module
SDRAM DIMM Block Diagram (2 Bank, 16Mx8 SDRAMs)
S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D1
S1
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D9
S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D2
S3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D10
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D11
NOTE : Exact DQ wiring may differ from that shown above
CK0 CLK : SDRAMs D0 -D1, D4 - D5, 3.3pF Cap
CK1 CLK : SDRAMs D8 - D9,D12 - D13, 3.3pF Cap
CK2 CLK : SDRAMs D2 - D3,D6 -D7, 3.3pF Cap
CK3 CLK : SDRAMs D10 - D11, D14 -D15, 3.3pF Cap
A0 - A11
BA0
BA1
RAS
CAS
CKE0
WE
A0 - A11 : SDRAMs D0 - D15
A13/BS0 : SDRAMs D0 - D15
A12/BS1 : SDRAMs D0 - D15
RAS : SDRAMs D0- D15
CAS : SDRAMs D0- D15
CKE : SDRAMs D0- D7
WE : SDRAMs D0- D15
*All resistor values are 10 ohms except as shown.
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D4
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D5
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D12
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D13
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D6
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D14
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D15
CKE1
VDD
10K
CKE : SDRAMs D8- D15
VDD
.33uF
VSS
D0 - D15
0.1 uF
D0 - D15
SCL
WP
47K
Serial PD
A0 A1 A2
SA0 SA1 SA2
SDA
Preliminary 10 / 2001
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.


3Pages


NT256S64V8HC0G 電子部品, 半導体
NT256S64V8HC0G
256MB : 32M x 64
Unbuffered SDRAM Module
Operating, Standby, and Refresh Currents (T A =0 to 70 °C , V DD =3.3 ± 0.3V)
Parameter
Symbol
Test condition
Operating current
ICC1
Precharge
standby current
in power-down mode
ICC2P
ICC2PS
Precharge
standby current in non
power-down mode
ICC2N
ICC2NS
No Operating current
( Active state : 4 bank)
ICC3P
ICC3N
Operating current
( Burst mode )
Auto(CBR)
refresh current
Self refresh current
Serial PD Device
Standby Current
ICC4
ICC5
ICC6
ISB
1 bank operation , tRC = tRC(mim), tCK = min
Active-Precharge Command cycling
without burst operation
CKE0 VIL (max), tCK = min,
S0 , S2 = VIH (min)
CKE0 VIL (max), tCK =oo,
S0 , S2 = VIH (min)
CKE0 VIH (min), tCK = min
S0 , S2 = VIH (min)
CKE0 VIH (min), tCK =oo,
S0 , S2 = VIH (min)
CKE0 VIL (max), tCK =min.
S0 , S2 = VIH (min) (Power Down Mode)
CKE0 VIH (min), tCK =min
S0 , S2 = VIH (min)
tCK =min , Read/ Write command cycling,
Multiple banks active, gapless data, BL=4
tCK =min, CBR command cycling
CKE0 0.2V
VIN = GND or VDD
Speed
- 7K - 75B - 8B
Unit
1200 1080 1080
mA
32 32 32 mA
32 32 32 mA
800 720 720 mA
144 144 144 mA
144 144 144 mA
960 800 800 mA
1560 1360 1360
mA
2000
32
30
1920
32
30
1920
32
30
mA
mA
µA
Serial PD Device Active
Power Supply Current
ICCA
SCL Clock Frequency=100 MHz
1 1 1 µA
1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I CC3N ).
2. The specified values are for both DIMM banks operating in the specified mode.
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC .
Input signals are changed up to three times during t RC (min).
4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during t CK(min) .
9. VDD =3.3V.
10. As follows:
• Input pulse levels V DD x 0.1 to V DD x 0.9
• Input rise and fall times 10ns
• Input and output timing levels V DD x 0.5
• Output load 1 TTL gate and CL=100pF
Note
1, 3,4
2
2
2,5
2,6
2,7
2,5
1,4,8
1
2
9
10
Preliminary 10 / 2001
6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

6 Page



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部品番号部品説明メーカ
NT256S64V8HC0G

256MB SDRAM Module

Nanya Technology
Nanya Technology


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