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BU-6184x の電気的特性と機能

BU-6184xのメーカーはData Deviceです、この部品の機能は「Enhanced Miniature Advanced Communications Engine」です。


製品の詳細 ( Datasheet PDF )

部品番号 BU-6184x
部品説明 Enhanced Miniature Advanced Communications Engine
メーカ Data Device
ロゴ Data Device ロゴ 




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BU-6184x Datasheet, BU-6184x PDF,ピン配置, 機能
BU-6174X/6184X/6186X
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
[ENHANCED MINI-ACE/µ-ACE (MICRO-ACE)]
µ-ACE
DESCRIPTION
The Enhanced Miniature Advanced Communications Engine (Enhanced
Mini-ACE) and µ-ACE (Micro-ACE) family of MIL-STD-1553 terminals pro-
vide complete interfaces between a host processor and a 1553 bus, and
integrate dual transceiver, protocol logic, and 4K or 64K words of RAM.
At 0.815" square, the µ-ACE (BGA package) option provides the
smallest footprint in the industry.
The terminals are powered by a choice of 5V or 3.3V logic.
Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, includ-
ing versions incorporating McAir compatible transmitters, is provided.
There is a choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT ver-
sions with 64K words of RAM include built-in RAM parity checking.
BC features include a built-in message sequence control engine, with
a set of 20 instructions. This feature provides an autonomous means
of implementing multi-frame message scheduling, message retry
schemes, data double buffering, asynchronous message insertion,
and reporting to the host CPU. The Enhanced Mini-ACE/µ-ACE incor-
porates a fully autonomous built-in self-test, providing comprehensive
testing of the internal protocol logic and/or RAM.
The RT offers the same choices of subaddress buffering as the ACE
and Mini-ACE (Plus), along with a global circular buffering option,
50% rollover interrupt for circular buffers, an interrupt status queue,
and an "Auto-boot" option to support MIL-STD-1760.
The terminals provide the same flexibility in host interface configura-
tions as the ACE/Mini-ACE, along with a reduction in the host proces-
sor's worst case holdoff time. Most software features are compatible
with the previous generations of the Mini-ACE (Plus) and ACE series.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Make sure the next
Card you purchase
has...
®
FEATURES
Fully Integrated 1553A/B Notice 2,
McAir, STANAG 3838 Interface Terminal
Compatible with Mini-ACE (Plus)
and ACE Generations
Choice of :
- RT or BC/RT/MT In Same Footprint
- RT or BC/RT/MT with 4K RAM
- BC/RT/MT with 64K RAM, and RAM
parity
Choice of 5V or 3.3V Logic
• Package Options:
- 1" Square Ceramic Flat Pack or
Gull Wing
- 0.815" Square BGA (µ-ACE)
5V Transceiver with 1760 and McAir
Compatible Options
Comprehensive Built-In Self-Test
Flexible Processor/Memory Interface,
with Reduced Host Wait Time
Choice of 10, 12, 16, or 20 MHz Clock
Highly Autonomous BC with
Built-In Message Sequence Control:
- Frame Scheduling
- Branching
- Asynchronous Message Insertion
- General Purpose Queue
- User-defined Interrupts
Advanced RT Functions
- Global Circular Buffering
- Interrupt Status Queue
- 50% Circular Buffer Rollover
Interrupts
Selective Message Monitor
- Selection by Address, T/R Bit,
Subaddress
- Command and Data Stacks
- 50% and 100% Stack Rollover
Interrupts
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
© 2000 Data Device Corporation

1 Page





BU-6184x pdf, ピン配列
TABLE 1. ENHANCED MINI-ACE/µ-ACE SERIES
SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +5V or +3.3V
RAM +5V
Transceiver +5V (Note 12)
Logic
Voltage Input Range for +5V
Logic (BU-61XX0/5)
Voltage Input Range for +3.3V
Logic (BU-61XX0/3/5)
MIN TYP MAX UNITS
-0.3 6.0 V
-0.3 6.0 V
-0.3 7.0 V
-0.3 6.0 V
-0.3 6.0 V
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
2.5
0.200
k
5 pF
0.860 Vp-p
10 Vpeak
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35 ,
Measured on Bus
Transformer Coupled Across
70 , Measured on Bus
(BU-61XXXXX-XX0,
BU-61XXXXX-XX2) (Note 13)
Output Noise, Diff (Direct Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
(BU-61XXXX3,
BU-61XXXX4)
6
18
20
-250
100
200
7
20
22
150
250
9 Vp-p
27 Vp-p
27 Vp-p
10 mVp-p
250 mVp
300 nsec
300 nsec
LOGIC
VIH
All signals except CLK_IN
CLK_IN
VIL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
IIH, IIL
All signals except CLK_IN
IIH (Vcc=5.25V, VIN=Vcc)
IIH (Vcc=5.25V, VIN=2.7V)
IIH (Vcc=3.6V, VIN=Vcc)
IIH (Vcc=3.6V, VIN=2.7V)
IIL (Vcc=5.25V, VIN=0.4V)
IIL (Vcc=3.6V, VIN=0.4V)
CLK_IN
IIH
IIL
VOH (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOH (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOL=max)
VOL (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOL=max)
IOL (Vcc=4.5V)
IOH (Vcc=4.5V)
IOL (Vcc=3.0V)
IOH (Vcc=3.0V)
2.1
0.8•Vcc
0.4
1.0
-10
-350
-10
-350
-350
-350
-10
-10
2.4
2.4
3.4
2.2
0.7
0.2•Vcc
V
V
V
V
V
V
10 µA
-50 µA
10 µA
-33 µA
-50 µA
-33 µA
10 µA
10 µA
V
V
0.4 V
0.4 V
mA
-3.4 mA
mA
-2.2 mA
Data Device Corporation
www.ddc-web.com
3
TABLE 1. ENHANCED MINI-ACE/µ-ACE SERIES
SPECIFICATIONS (CONT.)
PARAMETER
LOGIC (CONT)
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
+5V (RAM for 61860/4/5),
Logic for BU-61XX5) (Note 12)
+3.3V (Logic for BU-61XX0/3/4)
(Note 12)
+5V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
BU-61865XX-XX0
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61865/0X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61864XX-XX0
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
BU-61864/0X3-XX2
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
BU-61745XX-XX0. BU-61845XX-XX0
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61745/0X3-XX2,
BU-61845/0X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61743XX-XX0, BU-61843XX-XX0
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
BU-61743/0X3-XX2,
BU-61843/0X3-XX2
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
MIN TYP MAX UNITS
50 pF
50 pF
4.5 5.0 5.5
3.0 3.3 3.6
4.75 5.0 5.25
V
V
V
116 180
217 285
318 390
519 600
mA
mA
mA
mA
116 180
228 296
340 412
563 645
mA
mA
mA
mA
66 120
163 225
260 330
454 540
25 40
mA
mA
mA
mA
mA
66 120
174 236
282 352
498 585
25 40
mA
mA
mA
mA
mA
116 160
222 265
328 370
540 580
mA
mA
mA
mA
116 160
233 276
350 392
584 625
mA
mA
mA
mA
65 100
169 205
273 310
481 520
25 40
mA
mA
mA
mA
mA
65 100
180 216
295 332
525 565
25 40
mA
mA
mA
mA
mA
BU-6174X/6184X/6186X
M-12/04-0


3Pages


BU-6184x 電子部品, 半導体
To minimize board space and "glue" logic, the Enhanced Mini-
ACE/µ-ACE terminals provide the same wide choice of host
interface configurations as the ACE and Mini-ACE (Plus). This
includes support of interfaces to 16-bit or 8-bit processors, mem-
ory or port type interfaces, and multiplexed or non-multiplexed
address/data buses. In addition, with respect to ACE/Mini-ACE
(Plus), the worst case processor wait time has been significant-
ly reduced. For example, assuming a 16 MHz clock, this time has
been reduced from 2.8 µs to 632 ns for read accesses, and to
570 ns for write accesses.
The Enhanced Mini-ACE series terminals operate over the full
military temperature range of -55 to +125°C. Available screened
to MIL-PRF-38534C, the terminals are ideal for military and
industrial processor-to-1553 applications.
TEST COMPONENTS
Daisy chain mechanical samples of the µ-ACE, 128-ball BGA
(BU-61863B3-601) are available. These are used to verify both
the electrical and mechanical integrity of the solder joints
between the BGA package and the board. Ball pairs are inter-
nally wired so that the user can test for electrical continuity
between balls. Refer to TABLE 57 for connection details.
Although these units are inert, they are fully populated with sili-
con die so that they closely match the thermal and mechanical
characteristics of standard production units. Internal daisy chain
interconnections are made by copper PWB traces.
BU-61860E3 MICRO-ACE (+5.0V) & TRANSFORMER
EVALUATION BOARD
The BU-61860E3 board is intended to support customers who
are interested in electrically connecting and evaluating the per-
formance of +5.0V Enhanced Mini-ACE and/or +5.0V Micro-ACE
series of products. The user will be able to quickly perform func-
tional tests and run their system software utilizing this relatively
small (2.0” x 2.5”) evaluation board.
As shown in FIGURE 2, the BU-61860E3 consists of a PC board
incorporating a +5.0V Micro-ACE (BU-61860B3, BC/RT/MT with
64K x 17 RAM), necessary decoupling capacitors, and associat-
ed isolation transformers. The MIL-STD-1760 outputs are user
configurable as either Stub (transformer) or Direct Coupling. The
board supports the signal fan-out of the +5.0V Micro-ACE to 112
pins subdivided into (4) dual inline, berg type pin rows. These
pins (0.025” square max) and their row placement adhere to
standard 0.100” vector board spacing.
TRANSCEIVERS
The transceivers in the Enhanced Mini-ACE/µ-ACE series termi-
nals are fully monolithic, requiring only a +5 volt power input.
The transmitters are voltage sources, which provide improved
line driving capability over current sources. This serves to
improve performance on long buses with many taps. The trans-
mitters also offer an option which satisfies the MIL-STD-1760
TABLE 2. ADDRESS MAPPING
ADDRESS LINES
REGISTER
DESCRIPTION/ACCESSIBILITY
A4 A3 A2 A1 A0
0 0 0 0 0 Interrupt Mask Register #1 (RD/WR)
0 0 0 0 1 Configuration Register #1 (RD/WR)
0 0 0 1 0 Configuration Register #2 (RD/WR)
0 0 0 1 1 Start/Reset Register (WR)
Non-Enhanced BC/RT Command Stack Pointer /
0 0 0 1 1 Enhanced BC Instruction List Pointer Register
(RD)
0
0
1
0
0
BC Control Word /
RT Subaddress Control Word Register (RD/WR)
0 0 1 0 1 Time Tag Register (RD/WR)
0 0 1 1 0 Interrupt Status Register #1 (RD)
0 0 1 1 1 Configuration Register #3 (RD/WR)
0 1 0 0 0 Configuration Register #4 (RD/WR)
0 1 0 0 1 Configuration Register #5 (RD/WR)
0 1 0 1 0 RT / Monitor Data Stack Address Register (RD)
0 1 0 1 1 BC Frame Time Remaining Register (RD)
0
1
1
0
0
BC Time Remaining to Next Message Register
(RD)
Non-Enhanced BC Frame Time / Enhanced BC
0 1 1 0 1 Initial Instruction Pointer / RT Last Command /
MT Trigger Word Register(RD/WR)
0 1 1 1 0 RT Status Word Register (RD)
0 1 1 1 1 RT BIT Word Register (RD)
1 0 0 0 0 Test Mode Register 0
1 0 0 0 1 Test Mode Register 1
1 0 0 1 0 Test Mode Register 2
1 0 0 1 1 Test Mode Register 3
1 0 1 0 0 Test Mode Register 4
1 0 1 0 1 Test Mode Register 5
1 0 1 1 0 Test Mode Register 6
1 0 1 1 1 Test Mode Register 7
1 1 0 0 0 Configuration Register #6 (RD/WR)
1 1 0 0 1 Configuration Register #7 (RD/WR)
1 1 0 1 0 RESERVED
1 1 0 1 1 BC Condition Code Register (RD)
1 1 0 1 1 BC General Purpose Flag Register (WR)
1 1 1 0 0 BIT Test Status Register (RD)
1 1 1 0 1 Interrupt Mask Register #2 (RD/WR)
1 1 1 1 0 Interrupt Status Register #2 (RD)
BC General Purpose Queue Pointer /
1 1 1 1 1 RT-MT Interrupt Status Queue Pointer Register
(RD/WR)
Data Device Corporation
BU-6174X/6184X/6186X
www.ddc-web.com
6
M-12/04-0

6 Page



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部品番号部品説明メーカ
BU-6184x

Enhanced Miniature Advanced Communications Engine

Data Device
Data Device


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