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PDF HD6417705 Data sheet ( Hoja de datos )
| Número de pieza | HD6417705 | |
| Descripción | MICROPROCESSOR | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD6417705 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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omTo all our customers
U.cRegarding the change of names mentioned in the document, such as
t4Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
SheeThe semiconductor operations of Mitsubishi Electric and Hitachi were
tatransferred to Renesas Technology Corporation on April 1st 2003.
aThese operations include microcomputer, logic, analog and discrete devices,
.Dand memory chips other than DRAMs (flash memory, SRAMs etc.)
w Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
w and other Hitachi brand names are mentioned in the document, these names
w have in fact all been changed to Renesas Technology Corp.
Thank you for your understanding. Except for our corporate trademark,
logo and corporate statement, no changes whatsoever have been made to the
mcontents of the document, and these changes do not constitute any alteration
to the contents of the document itself.
.coRenesas Technology Home Page: www.renesas.com
et4URenesas Technology Corp.
Customer Support Dept.
www.DataSheApril 1, 2003
Renesas Technology Cwowrpw..DataSheet4U.com
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Index
Rev. 1.0, 11/02, page iv of xxxviii
5 Page 
3.3.2 TLB Indexing....................................................................................................... 77
3.3.3 TLB Address Comparison ................................................................................... 78
3.3.4 Page Management Information............................................................................ 80
3.4 MMU Functions................................................................................................................ 81
3.4.1 MMU Hardware Management ............................................................................. 81
3.4.2 MMU Software Management .............................................................................. 81
3.4.3 MMU Instruction (LDTLB)................................................................................. 82
3.4.4 Avoiding Synonym Problems .............................................................................. 83
3.5 MMU Exceptions.............................................................................................................. 85
3.5.1 TLB Miss Exception ............................................................................................ 85
3.5.2 TLB Protection Violation Exception ................................................................... 86
3.5.3 TLB Invalid Exception ........................................................................................ 87
3.5.4 Initial Page Write Exception ................................................................................ 88
3.6 Memory-Mapped TLB...................................................................................................... 90
3.6.1 Address Array ...................................................................................................... 90
3.6.2 Data Array ........................................................................................................... 90
3.6.3 Usage Examples................................................................................................... 92
3.7 Usage Note........................................................................................................................ 92
Section 4 Cache .................................................................................................93
4.1 Features............................................................................................................................. 93
4.1.1 Cache Structure.................................................................................................... 93
4.2 Register Descriptions ........................................................................................................ 95
4.2.1 Cache Control Register 1 (CCR1) ....................................................................... 96
4.2.2 Cache Control Register 2 (CCR2) ....................................................................... 97
4.2.3 Cache Control Register 3 (CCR3) ....................................................................... 100
4.3 Operation .......................................................................................................................... 101
4.3.1 Searching the Cache............................................................................................. 101
4.3.2 Read Access......................................................................................................... 102
4.3.3 Prefetch Operation ............................................................................................... 102
4.3.4 Write Access ........................................................................................................ 102
4.3.5 Write-Back Buffer ............................................................................................... 103
4.3.6 Coherency of Cache and External Memory ......................................................... 103
4.4 Memory-Mapped Cache ................................................................................................... 104
4.4.1 Address Array ...................................................................................................... 104
4.4.2 Data Array ........................................................................................................... 105
4.4.3 Usage Examples................................................................................................... 107
4.5 Usage Note........................................................................................................................ 108
Section 5 Exception Handling ...........................................................................109
5.1 Register Descriptions ........................................................................................................ 109
5.1.1 TRAPA Exception Register (TRA) ..................................................................... 110
Rev. 1.0, 11/02, page x of xxxviii
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6417705.PDF ] | |
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