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UPD44165184 の電気的特性と機能

UPD44165184のメーカーはNECです、この部品の機能は「(UPD44165084/184/364) 18M-BIT QDRII SRAM 4-WORD BURST OPERATION」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD44165184
部品説明 (UPD44165084/184/364) 18M-BIT QDRII SRAM 4-WORD BURST OPERATION
メーカ NEC
ロゴ NEC ロゴ 




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UPD44165184 Datasheet, UPD44165184 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44165084, 44165184, 44165364
18M-BIT QDRTMII SRAM
4-WORD BURST OPERATION
Description
The µPD44165084 is a 2,097,152-word by 8-bit, the µPD44165184 is a 1,048,576-word by 18-bit and the
µPD44165364 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The µPD44165084, µPD44165184 and µPD44165364 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with µs restart
User programmable impedance output
Fast clock cycle time : 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15825EJ7V1DS00 (7th edition)
Date Published July 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2001

1 Page





UPD44165184 pdf, ピン配列
µPD44165084, 44165184, 44165364
Pin Configurations
/××× indicates active low signal.
165-pin PLASTIC BGA (13 x 15)
(Top View)
[µPD44165084F5-EQ1]
1 2 3 4 5 6 7 8 9 10 11
A /CQ
VSS
A
/W /NW1 /K NC /R
A VSS CQ
B NC NC NC A NC K /NW0 A NC NC Q3
C NC NC NC VSS A NC A VSS NC NC D3
D NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC
H /DLL
VREF
VDDQ VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0
M NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N NC D7 NC VSS
A
A
A VSS NC NC NC
P NC NC Q7
A
A
C
A
A NC NC NC
R TDO TCK
A
A
A /C
A
A
A TMS TDI
A
D0 to D7
Q0 to Q7
/R
/W
/NW0, /NW1
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
Remark Refer to Package Drawing for the index mark.
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Data Sheet M15825EJ7V1DS
3


3Pages


UPD44165184 電子部品, 半導体
µPD44165084, 44165184, 44165364
Pin Identification
Symbol
A
D0 to Dxx
Q0 to Qxx
/R
/W
/BWx
/NWx
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on future
devices. All transactions operate on a burst of four words (two clock periods of bus activity). These inputs are
ignored when device is deselected.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K
during WRITE operations. See Pin Configurations for ball site location of individual signals.
x8 device uses D0 to D7.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges
if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site
location of individual signals.
x8 device uses Q0 to Q7.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be
initiated. This input must meet setup and hold times around the rising edge of K and is ignored on the
subsequent rising edge of K.
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be
initiated. This input must meet setup and hold times around the rising edge of K and is ignored on the
subsequent rising edge of K.
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous
inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
/C is used as the output timing reference for first and third output data. The rising edge of C is used as the
output reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C
may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and
/C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation.
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. This pin cannot be connected directly to GND or left unconnected. Also, in this product, there is no
function to minimize the output impedance by connecting ZQ directly to VDDQ.
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
IEEE 1149.1 Test Output: 1.8V I/O level.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics
and Operating Conditions for range.
Power Supply: Ground
No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level
applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.
6 Data Sheet M15825EJ7V1DS

6 Page



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共有リンク

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部品番号部品説明メーカ
UPD44165182

(UPD44165082/182/362) 18M-BIT QDRII SRAM 2-WORD BURST OPERATION

NEC
NEC
UPD44165184

(UPD44165084/184/364) 18M-BIT QDRII SRAM 4-WORD BURST OPERATION

NEC
NEC


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