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EX256 の電気的特性と機能

EX256のメーカーはActelです、この部品の機能は「eX Family FPGAs」です。


製品の詳細 ( Datasheet PDF )

部品番号 EX256
部品説明 eX Family FPGAs
メーカ Actel
ロゴ Actel ロゴ 




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EX256 Datasheet, EX256 PDF,ピン配置, 機能
eX Family FPGAs
v4.2
FuseLock
Leading Edge Performance
• 240 MHz System Performance
• 350 MHz Internal Performance
• 3.9 ns Clock-to-Out (Pad-to-Pad)
Specifications
• 3,000 to 12,000 Available System Gates
• Maximum 512 Flip-Flops (Using CC Macros)
• 0.22µm CMOS Process Technology
• Up to 132 User-Programmable I/O Pins
Features
• High-Performance, Low-Power Antifuse FPGA
• LP/Sleep Mode for Additional Power Savings
• Advanced Small-Footprint Packages
• Hot-Swap Compliant I/Os
• Single-Chip Solution
• Nonvolatile
• Live on Power-Up
• No Power-Up/Down Sequence Required for Supply
Voltages
• Configurable Weak-Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
• Individual Output Slew Rate Control
• 2.5V, 3.3V, and 5.0V Mixed-Voltage Operation
with 5.0V Input Tolerance and 5.0V Drive Strength
• Software Design Support with Actel Designer and
Libero™ Integrated Design Environment (IDE)
Tools
• Up to 100% Resource Utilization with 100% Pin
Locking
• Deterministic Timing
• Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Fuselock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Product Profile
Device
eX64
eX128
Capacity
System Gates
Typical Gates
3,000
2,000
6,000
4,000
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64 128
128 256
Combinatorial Cells
128 256
Maximum User I/Os
84 100
Global Clocks
Hardwired
Routed
11
22
Speed Grades
–F, Std, –P
–F, Std, –P
Temperature Grades*
C, I, A
C, I, A
Package (by pin count)
TQFP
CSP
64, 100
49, 128
64, 100
49, 128
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
eX256
12,000
8,000
256
512
512
132
1
2
–F, Std, –P
C, I, A
100
128, 180
June 2004
© 2004 Actel Corporation
i

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EX256 pdf, ピン配列
Table of Contents
eX Family FPGAs
eX Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2.5V/3.3V/5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
5.0V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Package Pin Assignments
64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
v4.1
iii


3Pages


EX256 電子部品, 半導体
eX Family FPGAs
Module Organization
C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells
and one R-cell in a C-R-C configuration.
Clusters are further organized into modules called SuperClusters for improved design efficiency and device
performance, as shown in Figure 1-3. Each SuperCluster is a two-wide grouping of Clusters.
D0
D1
Y
D2
D3
Sa Sb
Figure 1-2 • C-Cell
DB
A0 B0
R-Cell
Routed
S0 Data Input S1
DirectConnect
Input
PSET
DQ
Y
D0
D1
D2
D3
HCLK
CLKA,
CLKB,
Internal Logic
CKS
CLR
CKP
DB
A1 B1
C-Cell
Y
Sa Sb
A0 B0
A1 B1
Figure 1-3 • Cluster Organization
Cluster
Cluster
SuperCluster
1-2 v4.2

6 Page



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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
EX256

eX Family FPGAs

Actel
Actel
EX256-xxx

eX Family FPGAs

Actel
Actel


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