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21041-PBのメーカーはDigitalです、この部品の機能は「PCI Ethernet LAN Controller」です。 |
部品番号 | 21041-PB |
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部品説明 | PCI Ethernet LAN Controller | ||
メーカ | Digital | ||
ロゴ | |||
このページの下部にプレビューと21041-PBダウンロード(pdfファイル)リンクがあります。 Total 5 pages
Digital Semiconductor 21041
m PCI Ethernet LAN Controller
t4U.co Product Brief
February 1996
Shee Description
ata The Digital Semiconductor 21041 PCI Ethernet LAN Controller is a single-chip
master, direct memory access (DMA) Ethernet LAN controller with a direct inter-
.D face to the PCI local bus. It supports full-duplex operation, and its unique design
w is optimized to reduce the host bus utilization.
w The 21041 is highly integrated to support 10BASE5, 10BASE-T, or 10BASE2
w network connections. It is a high-performance device designed for PCI-based sys-
tems. The 21041 provides a direct interface to a 64KB, 128KB or 256KB boot
mROM. It supports both PCI 3.3-volt and 5.0-volt signaling environments and a
power-down mode for energy conservation. The 21041 is supported by a variety
oof software drivers and therefore offers a complete solution for all the leading net-
.cworking environments.
Features
U• Offers a single-chip Ethernet control-
ler for PCI local bus:
t4- Provides glueless connection to PCI
bus
- Contains an onchip integrated attach-
ement unit interface (AUI) port and a
e10BASE-T transceiver
• Implements the same architecture as
hthe 21040 to allow use of unified driv-
ers*
S• Supports full-duplex operation and
IEEE 802.3 autonegotiation algorithm
taof full-duplex and half-duplex net-
work environments*
a• Provides upgradable boot ROM (flash
or EEPROM) interface of 64KB,
128KB, or 256KB*
.D• Contains MicroWire EEPROM inter-
face for Ethernet ID address and, op-
tionally, other system parameters*
w - Implements automatic loading of
subsystem vendor ID and subsystem
w ID from serial ROM to distinguish
between different adapters based on
w mthe 21041 chip*
.co• Provides PCI clock speed up to
33 MHz, with no wait states on PCI
Umaster operation
et4• Enables powerful onchip DMA with
eprogrammable burst sizes up to 32
hlongwords, providing for low CPU
utilization
taS• Implements unique, patent-pending in-
atelligent arbitration between DMA
channels preventing underflow or
.Doverflow and optimized for full-
wwwduplex operation
• Incorporates a 16-bit, general-purpose
timer*
• Contains two large (256-byte) inde-
pendent receive and transmit FIFOs
• Supports either big-endian or little-
endian byte ordering
• Implements JTAG compatible test-
access port with boundary-scan pins
• Provides full support of IEEE 802.3,
ANSI 8802-3, and Ethernet standards
• Offers a unique, patented solution to
Ethernet capture-effect problem
• Contains a variety of flexible address
filtering modes
• Supports seven LEDs: Receive, Re-
ceive Address Match, Transmit,
Transmit Jabber, Collision, LinkPass,
and Polarity*
• Enables automatic detection and cor-
rection of 10BASE-T receive polarity
• Enables full autosensing between
10BASE-T, 10BASE2, and 10BASE5
ports*
• Provides external and internal loop-
back capability
• Contains 3.3-V CMOS device which
interfaces to 5.0-V or 3.3-V logic
• Provides a software-controllable
power-saving mode*
• Supports PCI 5.0-V and 3.3-V signal-
ing environments*
*21041 feature enhancements that are
not available in the 21040.
1 Page Figure 2 PCI-to-Ethernet Adapter Card
PCI Bus Connector
Ethernet ID
ROM
AUI
Digital Semiconductor
21041
PCI Ethernet LAN
Controller
Boot ROM
TP Line Driver
10BASE2 10BASE5
Figure 3 PCI Motherboard System
10BASE−T
PCI−Based
CPU
Memory Bus
Optional
Cache
PCI Bus
DRAM
Memory
PCI Slot 0
PCI Slot 1
SCSI
Controller
Digital Semiconductor
21041
PCI Ethernet LAN
Controller
Video
Subsystem
Bus Drivers
TP/AUI
Video Out
3Pages | |||
ページ | 合計 : 5 ページ | ||
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PDF ダウンロード | [ 21041-PB データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
21041-PB | PCI Ethernet LAN Controller | Digital |