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PDF MX29LV033A Data sheet ( Hoja de datos )
| Número de pieza | MX29LV033A | |
| Descripción | 32M-Bit CMOS Flash Memory | |
| Fabricantes | Macronix | |
| Logotipo |  |
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t4U.com MX29LV033A32M-BIT[4Mx8]CMOSEQUALSECTORFLASHMEMORY
SheeFEATURES
ataGENERAL FEATURES
.D• 4,194,304 x 8 byte structure
• Sixty-four Equal Sectors with 64KB each
w- Any combination of sectors can be erased with erase
wsuspend/resume function
w • Eighteen Sector Groups
m- Provides sector group protect function to prevent pro-
gram or erase operation in the protected sector group
o- Provides chip unprotected function to allow code
.cchanging
- Provides temporary sector group unprotected func-
tion for code changing in previously protected sector
Ugroups
• Single Power Supply Operation
t4- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• Latch-up protected to 250mA from -1V to Vcc + 1V
e• Low Vcc write inhibit is equal to or less than 1.4V
e• Compatible with JEDEC standard
- Pinout and software compatible to single power sup-
hply Flash
• 2nd generation of 3V/32M Flash product
S- Fully compatible with MX29LV033 device
taPERFORMANCE
• High Performance
a- Fast access time: 70/90ns
- Fast program time: 7us/byte, 36s/chip (typical)
.D- Fast erase time: 0.7s/sector, 35s/chip (typical)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 200nA (typical)
• Minimum 100,000 erase/program cycle
• 10-year data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
• Status Reply
- Data# polling & Toggle bits provide detection of pro-
gram and erase operation completion
• Support Command Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state
machine to read mode
• ACC input pin
- Provides accelerated program capability
PACKAGE
• 40-pin TSOP
wwGENERAL DESCRIPTION
mThe MX29LV033A is a 32-mega bit Flash memory orga-
w onized as 4M bytes of 8 bits. MXIC's Flash memories
.coffer the most cost-effective and reliable read/write non-
Uvolatile random access memory. The MX29LV033A is
t4packaged in 40-pin TSOP. It is designed to be repro-
egrammed and erased in system or in standard EPROM
eprogrammers.
ShThe standard MX29LV033A offers access time as fast
taas 70ns, allowing operation of high-speed microproces-
asors without wait states. To eliminate bus contention, the
.DMX29LV033A has separate chip enable (CE#) and out-
put enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV033A uses a command register to manage this
functionality.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LV033A uses a 2.7V to 3.6V VCC
wwwP/N:PM1017
REV. 1.0, SEP. 20, 2004
1
1 page  
MX29LV033A
SECTOR (GROUP) STRUCTURE
Group
SGA0
SGA1
SGA1
SGA1
SGA2
SGA2
SGA2
SGA2
SGA3
SGA3
SGA3
SGA3
SGA4
SGA4
SGA4
SGA4
SGA5
SGA5
SGA5
SGA5
SGA6
SGA6
SGA6
SGA6
SGA7
SGA7
SGA7
SGA7
SGA8
SGA8
SGA8
SGA8
SGA9
SGA9
SGA9
SGA9
SGA10
SGA10
SGA10
SGA10
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
A21 A20 A19 A18 A17 A16 Address Range(in hexadecimal)
0 0 0 0 0 0 000000-00FFFF
0 0 0 0 0 1 010000-01FFFF
0 0 0 0 1 0 020000-02FFFF
0 0 0 0 1 1 030000-03FFFF
0 0 0 1 0 0 040000-04FFFF
0 0 0 1 0 1 050000-05FFFF
0 0 0 1 1 0 060000-06FFFF
0 0 0 1 1 1 070000-07FFFF
0 0 1 0 0 0 080000-08FFFF
0 0 1 0 0 1 090000-09FFFF
0 0 1 0 1 0 0A0000-0AFFFF
0 0 1 0 1 1 0B0000-0BFFFF
0 0 1 1 0 0 0C0000-0CFFFF
0 0 1 1 0 1 0D0000-0DFFFF
0 0 1 1 1 0 0E0000-0EFFFF
0 0 1 1 1 1 0F0000-0FFFFF
0 1 0 0 0 0 100000-10FFFF
0 1 0 0 0 1 110000-11FFFF
0 1 0 0 1 0 120000-12FFFF
0 1 0 0 1 1 130000-13FFFF
0 1 0 1 0 0 140000-14FFFF
0 1 0 1 0 1 150000-15FFFF
0 1 0 1 1 0 160000-16FFFF
0 1 0 1 1 1 170000-17FFFF
0 1 1 0 0 0 180000-18FFFF
0 1 1 0 0 1 190000-19FFFF
0 1 1 0 1 0 1A0000-1AFFFF
0 1 1 0 1 1 1B0000-1BFFFF
0 1 1 1 0 0 1C0000-1CFFFF
0 1 1 1 0 1 1D0000-1DFFFF
0 1 1 1 1 0 1E0000-1EFFFF
0 1 1 1 1 1 1F0000-1FFFFF
1 0 0 0 0 0 200000-20FFFF
1 0 0 0 0 1 210000-21FFFF
1 0 0 0 1 0 220000-22FFFF
1 0 0 0 1 1 230000-23FFFF
1 0 0 1 0 0 240000-24FFFF
1 0 0 1 0 1 250000-25FFFF
1 0 0 1 1 0 260000-26FFFF
1 0 0 1 1 1 270000-27FFFF
P/N:PM1017
REV. 1.0, SEP. 20, 2004
5
5 Page 
MX29LV033A
DATA PROTECTION
The MX29LV033A is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorporates
several features to prevent inadvertent write cycles re-
sulting from VCC power-up and power-down transition or
system noise.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL, CE#
= VIH or WE# = VIH. To initiate a write cycle CE# and
WE# must be a logical zero while OE# is a logical one.
POWER-UP SEQUENCE
The MX29LV033A powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command se-
quences.
POWER-UP WRITE INHIBIT
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
P/N:PM1017
11
REV. 1.0, SEP. 20, 2004
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX29LV033A.PDF ] | |
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