DataSheet.jp

CS8552 の電気的特性と機能

CS8552のメーカーはMyson Technologyです、この部品の機能は「TV Encoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 CS8552
部品説明 TV Encoder
メーカ Myson Technology
ロゴ Myson Technology ロゴ 




このページの下部にプレビューとCS8552ダウンロード(pdfファイル)リンクがあります。

Total 25 pages

No Preview Available !

CS8552 Datasheet, CS8552 PDF,ピン配置, 機能
eet4U.com TV Encoder CS8552GENERAL DESCRIPTION
hThe CS8552 provides full conversion from digital
Svideo format YCbCr into NTSC/PAL composite and
taS-video. It can be used in VCD, DVD, and digital
aVCR applications.
.DTwo times oversampling reduces the output filter
wrequirements and guarantees no alias interference
wby internal UV filters and Y filter.
w Two 9-bit DACs provide two channels for a S-
FEATURES
• Especially designed for VCD, Karaoke, digital
VCR, DVD, DIGITAL set-top box.
• Supports the following 4 modes:
NTSC, PAL-M, PAL-BDGHI, PAL-Nc.
• 8-bit 4:2:2 YCbCr inputs for glueless interface to
MPEG decoders.
• CVBS (composite YC) or S-video (Y and C)
outputs.
video output port or two composite video outputs with
high quality image.
32-pin package and pin assignment make the
U.comCS8552 compatible with major vendors.
• Supports CCIR-601 format, non-square pixel
• 2x oversampling simplifying external filtering.
• 6MHz and 1.3MHz anti-alias filters for Y and U/V
channels each.
• 2 channels of 9-bit DAC.
• Supports master and slave modes.
• Supports interlace operation only.
• Automatic mode detection/switching in slave
mode.
• 3.3V supply voltage; 5V tolerant for all digital I/O
pins.
heet4BLOCK DIAGRAM
SH, V-SYNC
ataCLK_27
SLEEP
www.DP[7:0]
VIDEO-TIMING
CONTROLLER
SUB-CARRIER
GENERATION
SINE-TABLE
SERIAL
TO
PARALLEL
4:2:2 to
4:4:4
INTER-
POLATION
u-FILTER
v-FILTER
COLOR-BURST
&
MODULATION
&
MIXER
DAC
DAC
CVBS/Y
CVBS/C
MODE[3:0]
mSVIDEO
.coMASTER
et4UCBSWAP
y-FILTER
DAC-
MAPPING
VREF_O
FSADJUST
COMP
taSheMyson Century, Inc.
aTaiwan:
.DNo. 2, Industry East Rd. III,
wScience-Based Industrial Park, Hsin-Chu, Taiwan
wwTel: 886-3-5784866 Fax: 886-3-5784349
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
www.myson.com.tw
Rev. 1.3 January 2003
page 1 of 25

1 Page





CS8552 pdf, ピン配列
CS8552
PIN DESCRIPTION
Name
I/O
CLK_27
I
VSYNC
I/O
HSYNC
I/O
P[7:0]
I
MD[3:0]
MASTER
CBSWAP
SVIDEO
SLEEP
FSADJUST
COMP
VREFO
VREFI/VRDAC
I
I
I
I
I
I
I
I
I
NC
CVBS/C
CVBS/Y
VAA
VDD
GND
AGND
NC
O
O
O
PLCC Pin No.
Description
29 Pixel clock, 27MHz, twice the Y sample rate
32 Vertical sync, output in master mode or input in slave mode, is synchronized
by CLK.
1 Horizontal sync, output in master mode or input in slave mode, is
synchronized by CLK too.
28-21
YCbCr pixel inputs (TTL compatible). Also, synchronized by CLK with
respect to the incoming HSYNC timing, the higher index corresponds to a
greater significance.
17-20
Configuration inputs
16 in 0: slave mode, h and v sync are inputs. 1: master mode, h and v sync are
outputs.
15 0: normal Cr, Cb sequence. 1: swaps Cr, Cb sequence
14 0: composite output same signal on both Y, C channels, 1: s-video output, Y,
C channels.
13 1: power down, reset 0: normal operation
5 Full scale adjust control pin. A resistor RSET is connected to GND. Used to
control the full-scale output current on analog outputs.
6 Compensation pin. A 0.1µF capacitor is used to bypass this pin to VCC.
8 Voltage reference output, typically 1.2V, may be used to connect to VREFI
input.
9 Voltage reference input, typically 1.235V. A 0.11µF capacitor must be used
to decouple this input to GND. DAC current switch reference input, connect
to VREFO output.
10 No connection
11 Composite output or chrominance
4 Composite output or luminance (with blanking and sync)
7 Analog power
31 Digital power
30 Digital ground
3, 12
Analog ground
2 No connection
page 3 of 25


3Pages


CS8552 電子部品, 半導体
CS8552
PIXEL INPUT/OUTPUT TIMING
1. Clk is 2x the luminance sampling rate (13.5 MHz) or 4x the chrominance sampling rate (6.75 MHz), all signals
are reference to rising edge.
2. In accordance with CCIR656, the input pixel pattern begins during the first clk period after the falling edge of
HSYNC (same for master mode and slave mode). The input pattern is Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2,
Y3,...... The input pin CBSWAP and md[3] (YCSWAP) could be used to swap cb, cr sequence and also y and
cb, cr sequence. See Figure 3 and Figure 4.
3. Pixel input range: See Table 4.
Y: 16-235 for normal range; 0-15, 236-255 are invalid. When Y value is between 0-15, clamp to 16; when
the Y value is between 236-255, Y is set to 235.
CbCr: 16-240 for normal range with 128 mapped to 0; 0-15, 241-255 are invalid. When Cb/Cr is between
0-15, clamp to 16; when Cb/Cr is 241 to 255, Cb/Cr is set to 240.
Table-4 75% amplitude, 100% saturated YCbCr color bars
element
Y
Cb
Cr
range
16-235
16-240
16-240
White
235
128
128
Yellow
162
44
142
Cyan
131
156
44
Green
112
72
58
Magenta
84
184
198
Red
65
100
212
Blue
35
212
114
black
16
128
128
CLK
HSYNC*
YCSWAP=0
P[7:0]/CBSWAP=0 cb0 y0 cr0 y1 cb2 y2 cr2 y3 cb4
P[7:0]/CBSWAP=1 cr0 y0 cb0 y1 cr2 y2 cb2 y3 cr4
YCSWAP=1
P[7:0]/CBSWAP=0 y0
cb0 y1 cr2
y2 cb2 y3
cr4 y4
P[7:0]/CBSWAP=1 y0 cr0 y1 cb1 y2 cr2 y3 cb4 y4
Figure-3 Master Mode
page 6 of 25

6 Page



ページ 合計 : 25 ページ
 
PDF
ダウンロード
[ CS8552 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
CS8552

TV Encoder

Century
Century
CS8552

TV Encoder

Myson Technology
Myson Technology
CS8553

TV Encoder

Myson Technology
Myson Technology


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap