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PDF HD64F2636 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2636 | |
| Descripción | (HD64F263x Series) 16-Bit Microcomputer | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Preface
This LSI has the internal 32-bit H8S/2600 CPU and includes a variety of peripheral functions
necessary for a system configuration. It serves as a high-performance microcomputer.
The built-in peripheral devices include a 16-bit timer pulse unit (TPU), a programmable pulse
generator (PPG), a watchdog timer unit (WDT), a serial communication interface (SCI), an A/D
converter, a motor control PWM timer (PWM), a PC brake controller and I/O ports. It also has an
internal data transfer controller (DTC), which performs high-speed data transfer without using the
CPU, thus enabling the use of the LSI as an embedded microcomputer in various advanced control
systems. Two types of internal ROM are available: flash memory (F-ZTAT™*) and mask ROM.
The LSI can be used flexibly in a wide range of applications from applied equipment with varied
specifications and early production models to full-scale mass-produced products.
Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8S/2636, H8S/2638 and
H8S/2639 in the design of application systems. Members of this audience are
expected to understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2636, H8S/2638, and H8S/2639 to the above audience.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed
description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the details of a register when its name is known
The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal
I/O Registers.
Example: Bit order: The MSB is on the left and the LSB is on the right.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachisemiconductor.com/
5 Page 
Section
9.11.2 Register
Configuration
Page
267
9.11.3 Pin Functions 270
Table 9-20 Port F
Pin Functions
12.1 Overview
395
12.1.1 Features
395
12.1.2 Block
Diagram
Figure 12-1 (a)
Block Diagram of
WDT0
12.2.2 Timer
Control/Status
Register (TCSR)
396
401
12.2.2 Timer
Control/Status
Register (TCSR)
403
404
Description
13th line changed as follows
Modes 4 to 6
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3,
which are automatically designated as bus control outputs (AS, RD, HWR,
and LWR) (in the 8-bit mode, pin PF3 is designated by PFDDR).
PF0/IRQ2 amended
The pin function is switched as shown below according to the bit PF0DDR.
2nd line
(Incorrect) (WDT0/WDT1*1)
(Correct) (WDT0/WDT1)
• WDT0 and WDT1 respectively allow eight and sixteen types*1 of counter
input clock to be selected
Note amended
Note: *1 Versions of the H8S/2636 and H8S/2638 other than the U-mask
and W-mask versions have eight types of counter input clock as
well as WDT0.
Note amended
Note: *2 In the U-mask and W-mask versions, ø in subactive and subsleep
modes operates as øSUB.
Description newly added to 4th line as follows
Bit 7—Overflow Flag (OVF)
In the interval timer mode, the OVF flag can be cleared in the interval timer
interrupt routine by writing 0 to OVF after reading TCSR when OVF is set to
1, in accordance with the conditions for clearing the OVF flag.
However, when attempting to poll the OVF flag when interval timer interrupts
are prohibited the OVF value will not be recognized as 1 (even though it is set
to 1) if there is a conflict between the timing used to set the OVF flag and the
timing used to read the OVF flag.
In such cases it is possible to completely satisfy the conditions for clearing the
OVF flag by reading OVF two or more times while its value is 1. In a situation
such as the above, the OVF flag should be read two or more times while its
value is 1 and then cleared.
WDT0 Input Clock Select Note amended
Notes: *2 In the U-mask and W-mask versions, ø in subactive and subsleep
modes operates as øSUB.
WDT1 Input Clock Select Note added and amended
Bit 4
PSS*2
Notes: *2 …………. These functions cannot be used with the other versions,
therefore PSS bit is reserved. 0 should be written when writing.
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet HD64F2636.PDF ] | |
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