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PDF HD64F2646 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2646 | |
| Descripción | (HD64F264x Series) 16-Bit Microcomputer | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note:
Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note:
Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.
5 Page 
Section
Page
15.3.2 Initialization 565 to
after Hardware
567
Reset
Bit Rate and Bit
Timing Settings
Description
Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing
setting must be made each time a CAN node begins communication. The baud rate and
bit timing settings are made in the bit configuration register (BCR).
Note:
BCR can be written to at all times, but should only be modified in configuration mode.
Settings should be made so that all CAN controllers connected to the CAN bus have the
same baud rate and bit width.
Refer to table 15.3 for the range of values that can be used as settings (TSEG1, TSEG2,
BRP, sample point, and SJW) for BCR.
Table 15-3 BCR Register Value Setting Ranges
Name
Time segment 1
Time segment 2
Baud rate prescaler
Sample point
Re-synchronization jump width
Abbreviation
TSEG1
TSEG2
BRP
SAM
SJW
Min.
Value
Max.
Value
B'0011 B'1111
B'001
B'111
B'000000 B'111111
B'0 B'1
B'00 B'11
Value Setting Ranges
• The value of SJW is stipulated in the CAN specifications.
3 ≥ SJW ≥ 0
• The minimum value of TSEG1 is stipulated in the CAN specifications.
TSEG1 > TSEG2
• The minimum value of TSEG2 is stipulated in the CAN specifications.
TSEG2 ≥ SJW
The following formula is used to calculate the baud rate.
Bit rate =
fCLK
2 × (BRP + 1) × (3 + TSEG1 + TSEG2)
Note: fCLK = φ (system clock)
The BCR value is used in the BRP, TSEG1, and TSEG2.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD64F2646.PDF ] | |
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