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PDF HD64F2668 Data sheet ( Hoja de datos )

Número de pieza HD64F2668
Descripción (HD64F266x Series) 16-Bit Microcontroller
Fabricantes Hitachi 
Logotipo Hitachi Logotipo



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No Preview Available ! HD64F2668 Hoja de datos, Descripción, Manual

U.comwww.DHaittaacShiHh1eH86eSBt84i/StU2HS6/.icD2n6og667lm4e6-FFC82-h6ZiSp6Te7MAriiceTroscomputer
eet4Hardware Manual
ww.DataShADE-602-257A
wRev. 2.0
04/05/2002
Hitachi, Ltd.
www.DataSheet4U.com

1 page




HD64F2668 pdf
Preface
The H8S/2668 Series are microcomputers (MCU) made up of the H8S/2600 CPU employing
Hitachi's original architecture as their cores, and the peripheral functions required to configure a
system.
The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with data transfer controller (DTC) bus masters, ROM and RAM memory, a
16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), an 8-bit timer (TMR), a
watchdog timer (WDT), a serial communication interface (SCI and IrDA), a 10-bit A/D converter,
an 8-bit D/A converter, and I/O ports as on-chip peripheral modules required for system
configuration.
A high functionality bus controller is also provided, enabling fast and easy connection of DRAM,
SDRAM and other kinds of memory.
A single-power flash memory (F-ZTATTM*) version and masked ROM version are available for
this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices with specifications that will most probably
change.
This manual describes this LSI's hardware.
Note: * F-ZTATTM is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev. 2.0, 04/02, page v of xxxii

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HD64F2668 arduino
7.5.7 Number of DTC Execution States........................................................................162
7.6 Procedures for Using DTC................................................................................................164
7.6.1 Activation by Interrupt.........................................................................................164
7.6.2 Activation by Software ........................................................................................164
7.7 Examples of Use of the DTC ............................................................................................165
7.7.1 Normal Mode.......................................................................................................165
7.7.2 Chain Transfer .....................................................................................................165
7.7.3 Chain Transfer when Counter = 0........................................................................166
7.7.4 Software Activation .............................................................................................168
7.8 Usage Notes ......................................................................................................................169
7.8.1 Module Stop Mode Setting ..................................................................................169
7.8.2 On-Chip RAM .....................................................................................................169
7.8.3 DTCE Bit Setting .................................................................................................169
Section 8 I/O Ports ............................................................................................ 171
8.1 Port 1.................................................................................................................................176
8.1.1 Port 1 Data Direction Register (P1DDR).............................................................176
8.1.2 Port 1 Data Register (P1DR)................................................................................176
8.1.3 Port 1 Register (PORT1)......................................................................................177
8.1.4 Pin Functions .......................................................................................................178
8.2 Port 2.................................................................................................................................186
8.2.1 Port 2 Data Direction Register (P2DDR).............................................................186
8.2.2 Port 2 Data Register (P2DR)................................................................................186
8.2.3 Port 2 Register (PORT2)......................................................................................187
8.2.4 Pin Functions .......................................................................................................188
8.3 Port 3.................................................................................................................................196
8.3.1 Port 3 Data Direction Register (P3DDR).............................................................196
8.3.2 Port 3 Data Register (P3DR)................................................................................197
8.3.3 Port 3 Register (PORT3)......................................................................................197
8.3.4 Port 3 Open Drain Control Register (P3ODR).....................................................198
8.3.5 Port Function Control Register 2 (PFCR2) ..........................................................198
8.3.6 Pin Functions .......................................................................................................199
8.4 Port 4.................................................................................................................................201
8.4.1 Port 4 Register (PORT4)......................................................................................201
8.5 Port 5.................................................................................................................................202
8.5.1 Port 5 Data Direction Register (P5DDR).............................................................202
8.5.2 Port 5 Data Register (P5DR)................................................................................202
8.5.3 Port 5 Register (PORT5)......................................................................................203
8.5.4 Pin Functions .......................................................................................................203
8.6 Port 6.................................................................................................................................206
8.6.1 Port 6 Data Direction Register (P6DDR).............................................................206
8.6.2 Port 6 Data Register (P6DR)................................................................................206
Rev. 2.0, 04/02, page xi of xxxii

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