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PDF HD64F2641 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2641 | |
| Descripción | (HD64F264x Series) 16-Bit Microcontroller | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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U.comwww.DataSheeHt48USHH.HHc/DD288o666SSm444//3322322666644S4432e32ries
t4H8S/2641
eHD6432641
eH8S/2643 F-ZTAT™
hHD64F2643
taSHardware Manual
ww.DaADE-602-214A
Rev. 2.0
w3/20/01
Hitachi, Ltd.
www.DataSheet4U.com
1 page  
Main Revisions and Additions in this Edition
Page
7
12
75
586
587
598
744
745
870, 871
896, 898
899, 901
930
932
965, 967,
972
Item Revisions (See Manual for Details)
1.3.1 Pin Arrangement
Figure 1-2 Pin Arrangement
Note 2 added
1.3.2 Pin Functions in Each
Operating Mode
Table 1-2 Pin Functions in Each Operating
Mode
Note 2 added
3.4 Pin Functions in Each
Operating Mode
Table 3-3 Pin Functions in Each Mode
PA3 to PA0, modes 4 and 5 of port B modified
and port G added
15.2.2 Timer Control/Status
Register
WDT0 Input Clock Select: Overflow Period of
ø/64, 8192, 32768 modified
WDT1 Input Clock Select: Overflow Period of
ø/64, 8192, 32768 modified
15.5.6 OVF Flag Clearing in
Interval Timer Mode
Added
18.3.9 Sample Flowcharts
Figure 18-14 Flowchart for Master Transmit
Mode modified
Figure 18-15 Flowchart for Master Receive
Mode modified
Section 22 ROM
Totally modified
24.1 Overview
Table 24-1 LSI Internal States in Each Mode
Note added
25.2 DC Characteristics
Table 25-2 DC Characteristics (1)
Note 5 added
Table 25-2 DC Characteristics (2)
Note 6 added
25.4 A/D Conversion
Characteristics
Table 25-11 A/D Conversion Characteristics:
Conversion time Min and Max values modified
25.6 Flash Memory Characteristics Table 25-14 Flash Memory Characteristics:
Erase time Typ value modified
A.2 Instruction Codes
CLRMAC, LDMAC, MAC, STMAC instructions
modified
5 Page 
7.5.8 Wait Control.......................................................................................................... 177
7.5.9 Byte Access Control ............................................................................................. 179
7.5.10 Burst Operation..................................................................................................... 181
7.5.11 Refresh Control..................................................................................................... 185
7.6 DMAC Single Address Mode and DRAM Interface ......................................................... 189
7.6.1 DDS=1 .................................................................................................................. 189
7.6.2 DDS=0 .................................................................................................................. 190
7.7 Burst ROM Interface.......................................................................................................... 191
7.7.1 Overview............................................................................................................... 191
7.7.2 Basic Timing......................................................................................................... 191
7.7.3 Wait Control.......................................................................................................... 193
7.8 Idle Cycle ........................................................................................................................... 194
7.8.1 Operation .............................................................................................................. 194
7.8.2 Pin States in Idle Cycle ......................................................................................... 198
7.9 Write Data Buffer Function ............................................................................................... 199
7.10 Bus Release........................................................................................................................ 200
7.10.1 Overview............................................................................................................... 200
7.10.2 Operation .............................................................................................................. 200
7.10.3 Pin States in External Bus Released State ............................................................ 201
7.10.4 Transition Timing ................................................................................................. 202
7.10.5 Notes ..................................................................................................................... 203
7.11 Bus Arbitration................................................................................................................... 204
7.11.1 Overview............................................................................................................... 204
7.11.2 Operation .............................................................................................................. 204
7.11.3 Bus Transfer Timing ............................................................................................. 205
7.12 Resets and the Bus Controller............................................................................................ 205
Section 8 DMA Controller .............................................................................................. 207
8.1 Overview............................................................................................................................ 207
8.1.1 Features ................................................................................................................. 207
8.1.2 Block Diagram...................................................................................................... 208
8.1.3 Overview of Functions.......................................................................................... 209
8.1.4 Pin Configuration.................................................................................................. 211
8.1.5 Register Configuration.......................................................................................... 212
8.2 Register Descriptions (1) (Short Address Mode)............................................................... 213
8.2.1 Memory Address Registers (MAR)...................................................................... 214
8.2.2 I/O Address Register (IOAR) ............................................................................... 215
8.2.3 Execute Transfer Count Register (ETCR)............................................................ 215
8.2.4 DMA Control Register (DMACR) ....................................................................... 216
8.2.5 DMA Band Control Register (DMABCR) ........................................................... 220
8.3 Register Descriptions (2) (Full Address Mode) ................................................................. 225
8.3.1 Memory Address Register (MAR)........................................................................ 225
8.3.2 I/O Address Register (IOAR) ............................................................................... 225
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD64F2641.PDF ] | |
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