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IS42S16400L PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS42S16400L
部品説明 (IS42S8800x/ IS42S16400x) 2M x 8-Bit x 4-Bank SDRAM
メーカ ISSI
ロゴ ISSI ロゴ 



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IS42S16400L Datasheet, IS42S16400L PDF,ピン配置, 機能
IS42S8800/IS42S8800L
I2SS(Y14N)M2CSHWR1oOr6hdeN4seO0tx4U0U8S/(.I1cSDo6m)4YBN2itASsM1xI6C44BR0aAn0MkLs (64-MBIT)FEATURES
taS• Single 3.3V (± 0.3V) power supply
a• High speed clock cycle time -7: 133MHz<3-3-3>,
.D-8: 100MHz<2-2-2>
w• Fully synchronous operation referenced to clock
wrising edge
w• Possible to assert random column access in
mevery cycle
• Quad internal banks contorlled by A12 & A13
o(Bank Select)
.c• Byte control by LDQM and UDQM for
IS42S16400
U• Programmable Wrap sequence (Sequential /
t4Interleave)
• Programmable burst length (1, 2, 4, 8 and full
epage)
• Programmable /CAS latency (2 and 3)
e• Automatic precharge and controlled precharge
h• CBR (Auto) refresh and self refresh
S• X8, X16 organization
• LVTTL compatible inputs and outputs
ta• 4,096 refresh cycles / 64ms
a• Burst termination by Burst stop and Precharge
command
.D• Package 400mil 54-pin TSOP-2
DESCRIPTION
The IS42S8800 and IS42S16400 are high-speed 67,
108,864-bit synchronous dynamic random-access
moeories, organized as 2,097,152 x 8 x 4 and 1,048,
576 x 16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data
transfer using the pipeline architecture and clock
frequency up to 133MHz for -7. All input and outputs
are synchronized with the postive edge of the clock.
The synchronous DRAMs are compatible with Low
Voltage TTL (LVTTL).These products are pack-aged
in 54-pin TSOP-2.
www .DataSheet4U.comICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
wwwIntegrated Circuit Solution Inc.
1
DR007-0A

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