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PDF IS42S8800L Data sheet ( Hoja de datos )
| Número de pieza | IS42S8800L | |
| Descripción | (IS42S8800x/ IS42S16400x) 2M x 8-Bit x 4-Bank SDRAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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IS42S8800/IS42S8800L
I2SS(Y14N)M2CSHWR1oOr6hdeN4seO0tx4U0U8S/(.I1cSDo6m)4YBN2itASsM1xI6C44BR0aAn0MkLs (64-MBIT)FEATURES
taS Single 3.3V (± 0.3V) power supply
a High speed clock cycle time -7: 133MHz<3-3-3>,
.D-8: 100MHz<2-2-2>
w Fully synchronous operation referenced to clock
wrising edge
w Possible to assert random column access in
mevery cycle
Quad internal banks contorlled by A12 & A13
o(Bank Select)
.c Byte control by LDQM and UDQM for
IS42S16400
U Programmable Wrap sequence (Sequential /
t4Interleave)
Programmable burst length (1, 2, 4, 8 and full
epage)
Programmable /CAS latency (2 and 3)
e Automatic precharge and controlled precharge
h CBR (Auto) refresh and self refresh
S X8, X16 organization
LVTTL compatible inputs and outputs
ta 4,096 refresh cycles / 64ms
a Burst termination by Burst stop and Precharge
command
.D Package 400mil 54-pin TSOP-2
DESCRIPTION
The IS42S8800 and IS42S16400 are high-speed 67,
108,864-bit synchronous dynamic random-access
moeories, organized as 2,097,152 x 8 x 4 and 1,048,
576 x 16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data
transfer using the pipeline architecture and clock
frequency up to 133MHz for -7. All input and outputs
are synchronized with the postive edge of the clock.
The synchronous DRAMs are compatible with Low
Voltage TTL (LVTTL).These products are pack-aged
in 54-pin TSOP-2.
www .DataSheet4U.comICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
wwwIntegrated Circuit Solution Inc.
1
DR007-0A
1 page  
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
V,,
V,,3
VI
VO
IO
PD
TOPT
TSTG
Supply Voltage (with respect to VSS)
0.5 to +4.6
Supply Voltage for Output (with respect to VSSQ) 0.5 to +4.6
Input Voltage (with respect to VSS)
0.5 to VDD+0.5
Output Voltage (with respect to VSSQ)
1.0 to VDDQ+0.5
Short circuit output current
50
Power Dissipation (TA = 25 °C)
1
Operating Temperature
0 to +70
Storage Temperature
65 to +150
V
V
V
V
mA
W
°C
°C
Notes:
1. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
DC RECOMMENDED OPERATING CONDITIONS
(At TA = 0 to +70°C unless otherwise noted)
Symbol
VDD
VDDQ
VSS
VSSQ
VIH
VIL
Parameter
Supply Voltage
Supply Voltage for DQ
Ground
Ground for DQ
High Level Input Voltage (all Inputs)
Low Level Input Voltage (all Inputs)
Min.
3.0
0
3.0
0
2.0
-0.3
Typ.
3.3
0
3.3
0
Max.
3.6
0
3.6
0
VDD + 0.3
+0.8
Unit
V
V
V
V
V
V
CAPACITANCE CHARACTERISTICS
(At TA = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V , unless otherwise note@)
Symbol
CIN
CCLK
CI/O
Parameter
Input Capacitance, address & control pin
Input Capacitance, CLK pin
Data Input/Output Capacitance
Min.
2.5
2.5
4.0
Max.
3.8
3.5
6.5
Unit
pF
pF
pF
Integrated Circuit Solution Inc.
DR007-0A
5
5 Page 
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
OPERATION COMMAND TABLE(1)
Current State Command
Idle
Row Active
Read
Write
Read With
Auto-
Precharge
DESL
NOP or BST
READ / READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP or BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Operation
NOP or Power-Down(2)
NOP or Power-Down(2)
Illegal(3)
Illegal(3)
Row Active
NOP
Refresh or Self-Refresh(4)
Mode Register Set
NOP
NOP
Begin read : Determine AP(5)
Begin write : Determine AP(5)
Illegal(3)
Precharge(6)
Illegal
Illegal
Continue burst to -> end Row active
Continue burst to -> end Row active
Burst stop -> Row active
Term burst, new read : Determine AP(7)
Term burst, start write : Determine AP(7, 8)
Illegal(3)
Term burst, precharging
Illegal
Illegal
Continue burst to end -> write recovering
Continue burst to end -> write recovering
Burst stop -> Row active
Term burst, start read : Determine AP(7, 8)
Term burst, new write : Determine AP(7)
Illegal(3)
Term burst, precharging(9)
Illegal
Illegal
Continue burst to end -> Precharging
Continue burst to end -> Precharging
Illegal
Illegal(11)
Illegal(11)
Illegal(3)
Illegal(11)
Illegal
Illegal
Integrated Circuit Solution Inc.
DR007-0A
CS RAS CAS WE Address
H X X XX
L H H XX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BR, RA
L L H L BA, A10
L L L HX
L L L L Op-Code
H X X XX
L H H HX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BR, RA
L L H L BA, A10
L L L HX
L L L L Op-Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BR, RA
L L H L BA, A10
L L L HX
L L L L Op-Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BR, RA
L L H L BA, A10
L L L HX
L L L L Op-Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BR, RA
L L H L BA, A10
L L L HX
L L L L Op-Code
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS42S8800L.PDF ] | |
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