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IS42S16400 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS42S16400
部品説明 1M-Bit x 16-Bit 4 4-Bank SDRAM
メーカ ISSI
ロゴ ISSI ロゴ 



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IS42S16400 Datasheet, IS42S16400 PDF,ピン配置, 機能
®
I1SSYM4Ne2CgSHBR1itO6shNe4xeO0t14U06USB.cDiotYsmNxA4MBICanRksAM(64-MBIT) ISSIFEATURES
S• Clock frequency: 166, 133, 100 MHz
ta• Fully synchronous; all signals referenced to a
.Dapositive clock edge
• Internal bank for hiding row access/precharge
ww• Single 3.3V power supply
w• LVTTL interface
m• Programmable burst length
o– (1, 2, 4, 8, full page)
.c• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
U• 4096 refresh cycles every 64 ms
t4• Random column address every clock cycle
e• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
eoperations capability
h• Burst termination by burst stop and precharge
command
S• Byte controlled by LDQM and UDQM
ta• Industrial temperature availability
a• Package: 400-mil 54-pin TSOP II
w.DPIN DESCRIPTIONS
wA0-A11
mBA0, BA1
w .coI/O0 to I/O15
UCLK
t4CKE
eeCS
hRAS
taSCAS
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
FINAL PRODUCTION
MAY 2001
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S16400 is organized
as 1,048,576 bits x 16-bit x 4-bank for improved
performance. ThesynchronousDRAMsachievehigh-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VCC
I/O0
VCCQ
I/O1
I/O2
GNDQ
I/O3
I/O4
VCCQ
I/O5
I/O6
GNDQ
I/O7
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 GND
53 I/O15
52 GNDQ
51 I/O14
50 I/O13
49 VCCQ
48 I/O12
47 I/O11
46 GNDQ
45 I/O10
44 I/O9
43 VCCQ
42 I/O8
41 GND
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 GND
WE
LDQM
UDQM
Vcc
GND
VccQ
GNDQ
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
.DaThis document contains TARGET SPECIFICATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
wwwIntegrated Silicon Solution, Inc. — 1-800-379-4774
1
TARGET SPECIFICATION Rev. C
05/04/01

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