DataSheet.jp

IN24LC04B の電気的特性と機能

IN24LC04BのメーカーはIK Semiconductorです、この部品の機能は「(IN24LC04B / IN24LC08B) 4K/8K 2.5V CMOS Serial EEPROMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN24LC04B
部品説明 (IN24LC04B / IN24LC08B) 4K/8K 2.5V CMOS Serial EEPROMs
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




このページの下部にプレビューとIN24LC04Bダウンロード(pdfファイル)リンクがあります。
Total 10 pages

No Preview Available !

IN24LC04B Datasheet, IN24LC04B PDF,ピン配置, 機能
m TECHNICAL DATA
t4U.co IN24LC04B/08B
4K/8tKaS2h.5eVe CMOS Serial EEPROMsDESCRIPTION
aIN24LC04B/08B is a 4K-or 8K-bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x
.D8 bit memory with a two wire serial interface. Low voltage design permits operation down to 2.5 volts with standby and
wactive currents of only 5µA and 1mA respectively. The IN24LC04B/08B also has a page-write capability for up to 16
wwbytes of data. The IN24LC04B/08B is available in the standard 8-pin DIP.
FEATURES
m• Single supply with operation down to 2.5V
o• Low power CMOS technology
.c- 1 mA active current typical
- 10 µA standby current typical at 5.5V
U- 5 µA standby current typical at 3.0V
t4• Organized as two or four blocks of 256 bytes (2x256x8) and
(4x256x8)
e• Two wire serial interface bus, I2C compatible
e• Schmitt trigger, filtered inputs for noise suppression
h• Output slope control to eliminate ground bounce
S• 100 kHz (2.5V) and 400 kHz (5V) compatibility
ta• Self-timed write cycle (including auto-erase)
a• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
.D• Hardware write protect for entire memory
• Can be operated as a serial ROM
w• Factory programming (QTP) available
w• ESD protection > 4,000V
w• 1,000,000 ERASE/WRITE cycles guaranteed*
m• Data retention > 200 years
.co• 8-pin DIP
t4U• Temperature range -40 to +85 oC
PACKAGE
TA = -40 ... +85 °C
Name
PINNING
Function
Vss Ground
SDA
Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
VCC
+2.5V to 5.5V Power Supply
AO, A1, A2 No Internal Connection
Pin Connection
A0 1
A1 2
8 Vcc
7 WP
eeA2 3
6 SCL
www.DataShVss 4
5 SDA
1

1 Page





IN24LC04B pdf, ピン配列
Figure 2. Bus timing Start/Stop
IN24LC04B/08B
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Output fall time from VIH min
to VIL max
Input filter spike suppres-sion
(SDA & SCL pins)
Write cycle time
Symbol
FCLK
THIGH
TLOW
TR
TF
THD:STA
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
TOF
TSP
TWR
STANDARD
MODE
Min Max
- 100
4000 -
4700 -
- 1000
- 300
4000 -
4700
0
250
4000
-
-
-
-
-
3500
4700 -
- 250
- 50
- 10
Vcc = 4.5 - 5.5V
FAST MODE
Min Max
- 400
600 -
1300
-
- 300
- 300
600 -
600 -
0-
100 -
600 -
- 900
1300
-
20+0.1CB 250
- 50
Units Remarks
kHz
ns
ns
ns Note 2
ns Note 2
After this period the
ns first clock pulse is
generated
Only relevant for
ns repeated START
condition
ns
ns
ns
ns Note 1
Time the bus must be
ns free before a new
transmission can start
ns
Note2,
CB100pF
ns Note 3
-
10
ms
Byte or Page
mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined
region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or
STOP conditions.
Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide
improved noise and spike suppression. This eliminates the need for a Ti specification for standard
operation.
3


3Pages


IN24LC04B 電子部品, 半導体
IN24LC04B/08B
Figure 5. Control Byte Allocation
WRITE OPERATION
Byte Write
Following the start condition from the master, the device code (4 bits), the block address (3 bits),
and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates
to the addressed slave receiver that a byte with a word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is
the word address and will be written into the address pointer of the IN24LC04B/08B. After
receiving another acknowledge signal from the IN24LC04B/08B the master device will transmit the
data word to be written into the addressed memory location. The IN24LC04B/08B acknowledges
again and the master generates a stop condition. This initiates the internal write cycle, and during
this time the IN24LC04B/08B will not generate acknowledge signals (see Figure 6).
Page Write
The write control byte, word address and the first data byte are transmitted to the IN24LC04B/08B
in the same way as in a byte write. But instead of generating a stop condition the master transmits
up to sixteen data bytes to the IN24LC04B/08B which are temporarily stored in the on-chip page
buffer and will be written into the memory after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address pointer bits are internally incremented by one.
The higher order seven bits of the word address remains constant. If the master should transmit
more than sixteen words prior to generating the stop condition, the address counter will roll over
and the previously received data will be overwritten. As with the byte write operation, once the stop
condition is received an internal write cycle will begin (see Figure 8).
Figure 6. Byte Write
6

6 Page



ページ 合計 : 10 ページ
 
PDF
ダウンロード
[ IN24LC04B データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IN24LC04

(IN24LC04/08) 8K 2.5V CMOS Serial EEPROMs

IK Semiconductor
IK Semiconductor
IN24LC04B

(IN24LC04B / IN24LC08B) 4K/8K 2.5V CMOS Serial EEPROMs

IK Semiconductor
IK Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap