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IN16C554 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IN16C554
部品説明 TQ Enhanced Quadruple 16C550 UART
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 

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IN16C554 Datasheet, IN16C554 PDF,ピン配置, 機能
m IN16C554PL/IN16C554TQ
o QUAD-UART
.c ASYNCHRONOUS COMMUNICATIONS ELEMENT
eet4U1. General Description
hIN16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter).
taSEach channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal
aFIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes.
.DEach channel performs serial-to-parallel conversion on data characters received from a peripheral device or a
wwMODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete
w status of the UART at any time during the functional operation. The Status information includes the type and condition
of the transfer operations being performed by the UART, as well as any error conditions such as parity, overrun, framing,
mand break interrupt.
oIN16C554 includes a programmable baud rate generator which is capable of dividing the timing reference clock input
.cby divisors of 1 to 216-1, and producing a 16x clock for driving the internal transmitter logic. Provisions are also
included to use this clock to drive the receiver logic.
UIN16C554 has complete MODEM-control capability and an interrupt system that can be programmed to the user’s
requirements, minimizing the computing required to handle the communication links.
et42. Features
ez In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the
hnumber of interrupts to CPU.
z Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
Sz Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial
tadata.
az Independently controlled transmit, receive, line status and data interrupts.
z Programmable Baud Rate Generators which allow division of any input reference clock by 1 to 216-1 and
.Dgenerate an internal 16X clock.
z Independent receiver clock input
wz Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
wz Fully programmable serial interface characteristics.
w- 5-, 6-, 7-, or 8-bit characters
- Even-, Odd-, or No-Parity bit
om- 1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, IN16C554 checks only one stop bit, no matter
.chow many they are)
t4Uz False start bit detection
ez Generates or Detects Line Break
hez Internal diagnostic capabilities : Loop-back controls for communications link fault isolation.
www.DataSz Full prioritized interrupt system controls
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