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IN16C554 の電気的特性と機能

IN16C554のメーカーはIK Semiconductorです、この部品の機能は「TQ Enhanced Quadruple 16C550 UART」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN16C554
部品説明 TQ Enhanced Quadruple 16C550 UART
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




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IN16C554 Datasheet, IN16C554 PDF,ピン配置, 機能
m IN16C554PL/IN16C554TQ
o QUAD-UART
.c ASYNCHRONOUS COMMUNICATIONS ELEMENT
eet4U1. General Description
hIN16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter).
taSEach channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal
aFIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes.
.DEach channel performs serial-to-parallel conversion on data characters received from a peripheral device or a
wwMODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete
w status of the UART at any time during the functional operation. The Status information includes the type and condition
of the transfer operations being performed by the UART, as well as any error conditions such as parity, overrun, framing,
mand break interrupt.
oIN16C554 includes a programmable baud rate generator which is capable of dividing the timing reference clock input
.cby divisors of 1 to 216-1, and producing a 16x clock for driving the internal transmitter logic. Provisions are also
included to use this clock to drive the receiver logic.
UIN16C554 has complete MODEM-control capability and an interrupt system that can be programmed to the user’s
requirements, minimizing the computing required to handle the communication links.
et42. Features
ez In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the
hnumber of interrupts to CPU.
z Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
Sz Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial
tadata.
az Independently controlled transmit, receive, line status and data interrupts.
z Programmable Baud Rate Generators which allow division of any input reference clock by 1 to 216-1 and
.Dgenerate an internal 16X clock.
z Independent receiver clock input
wz Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
wz Fully programmable serial interface characteristics.
w- 5-, 6-, 7-, or 8-bit characters
- Even-, Odd-, or No-Parity bit
om- 1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, IN16C554 checks only one stop bit, no matter
.chow many they are)
t4Uz False start bit detection
ez Generates or Detects Line Break
hez Internal diagnostic capabilities : Loop-back controls for communications link fault isolation.
www.DataSz Full prioritized interrupt system controls
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IN16C554 pdf, ピン配列
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NAME
IOW#
PIN NO. I/O
DESCRIPTION
18 (31) I
Write strobe. IOW# allows the CPU to write into the selected address by the address register.
RESET 37 (53)
I
Master reset. When active, RESET clears most UART registers and sets the state of various
signals. The transmitter output and he receiver input is disabled during reset time.
RI0#,
RI1#
RI2#,
RI3#
8, 28
(18,43)
42, 62 (58,
3)
I
Ring detect indicator. A low on Rix# indicates the modem has received a ring signal from the
telephone line. The condition of this signal can be
checked by reading bit 6 of the modem status register.
RTS0#,
RTS1#
RTS2#,
RTS3#
14, 22
(26,35)
48, 56
(66,75)
O Request to Send. When active, RTSx# informs the modem or data set that the UART is ready
to receive data. Writing a 1 in the modem control register sets this bit to a low state. After
reset, this terminal is set high. These terminals have no affect on the transmit or receive
operation.
RXD0,
RXD1
RXD2,
RXD3
7, 29 (17,
44)
41, 63 (57,
4)
I
Serial Input. RXDx is a serial data input from a connected communications device. During
loopback mode, the RXDx input is disabled from external connection and connected to the
TXDx output internally.
RXRDY
#
38 (54)
O Receive ready. RXRDY# goes low when the receive FIFO is full. It can be used as a single
transfer or multi transfer.
TXD0,
TXD1
TXD2,
TXD3
17, 19
(29,32)
51, 53
(69,72)
Transmit output. TXDx is a composite serial data output that is connected to a
O communications device. TXD1, TXD2, TXD3, and TXD4 are set to the high state as a result
of reset.
TXRDY
#
VCC
XTAL1
39 (55) O
13, 30 (5,
25)
47, 64
(45,65)
35 (50)
I
Transmit Ready. TXRDY# goes low when the transmit FIFO is full. It can be used as a single
transfer of multi transfer.
Power supply.
Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to
utilize the internal oscillator circuit. An external clock can be connected to drive the internal
clock circuits.
XTAL2 36 (51) O Crystal output 2 or buffered clock output.
At the PIN NO, the number outside the parenthesis means the pin number of the IN16C554PL, and the number inside the parenthesis
means the pin number of the IN16C554TQ.
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IN16C554 電子部品, 半導体
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.1. FIFO control register(FCR)
The FCR is a write-only register at the same address as the IIR. FCR enables FIFO, sets the trigger level of the
receiver FIFO, and selects the type of DMA signaling.
z Bit 0 : FCR0 enables transmit and receiver FIFOs. All bytes in both FIFOs can be cleared by clearing this bit.
Data is cleared automatically from the FIFOs when changing from the FIFO mode to the 16C550 mode and
vice versa. Programming of other FCR bits is enabled by setting this bit.
z Bit 1 : When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the shift
register.
z Bit 2 : When set, FRC2 clears all bytes in the transmitter FIFO and resets its counter. This does not clear the
shift register.
z Bit 3 : When set, FRC3 changes RXRDY# and TXRDY# from mode 0 to mode 1 if FCR0 is set.
z Bit 4, 5 : Reserved for the future use.
z Bit 6, 7 : FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt. (see Table 1).
Table 1. Receiver FIFO Trigger Level
BIT Receiver FIFO
76
00
Trigger Level
01
01
04
10
08
11
14
* FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled.
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.
2. Receiver line status interrupt(IIR = 06) has higher priority than the receive data available interrupt(IIR = 04).
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4. Receive data available indicator(IIR=04) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are enabled.
1. When the following conditions exist, a FIFO character time-out interrupt occurs.
a. Minimum of one character in FIFO.
b. Last received serial character is longer than four continuous previous character times ago. (If two stop bits
are programmed, the second one is included in the time delay. Only the first stop bit is checked by the
UART.)
c. The last CPU of the FIFO read is more than four continuous character times earlier.
2. By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional to
the baud rate.
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共有リンク

Link :


部品番号部品説明メーカ
IN16C554

TQ Enhanced Quadruple 16C550 UART

IK Semiconductor
IK Semiconductor
IN16C554A

Quadruple UART

IK Semiconductor
IK Semiconductor


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