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IN82C55 の電気的特性と機能

IN82C55のメーカーはIK Semiconductorです、この部品の機能は「Promrammable Periphral Interface」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN82C55
部品説明 Promrammable Periphral Interface
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




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IN82C55 Datasheet, IN82C55 PDF,ピン配置, 機能
m TECHNICAL DATA
U.co IN82C55
eet4CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
taShThe Integral IN82C55AN is a high-performance, CHMOS version of the industry standard
aIN82C55AN general purpose programmable I/O device which is designed for use with all Intel and
.Dmost other microprocessors. It provides 24 I/O pins which may be individually programmed in 2
wgroups of 12 and used in 3 major modes of operation.
wwIn MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or
outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the
remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-
directional bus configuration.
.comFEATURES
Compatible with all Intel and Most Other Microprocessors
High Speed, «Zero Wait State» Operation with 8MHz 8086/88 and 80186/188
U24 Programmable I/O Pins
t4Low Power CHMOS
Completely TTL Compatible
Control Word Read-Back Capability
eDirect Bit Set/Reset Capability
e2.5mA DC Drive Capability on all I/O Port Outputs
Available in 40-Pin DIP
hAvailable in EXPRESS
ƒ Standard Temperature Range
Sƒ Extended Temperature Range
taƒ
aGROUP
A
CONTROL
www.DD7-D0
DATA
BUS
BUFFER
8 BIT
INTERNAL
DATA BUS
.comRD
UWR
t4A1
eA0
eReset
hCS
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
www.DataSFigure 1
GROUP
A
PORT
A
(8)
GROUP
A
PORT C
UPPER
(4)
GROUP
B
PORT C
LOWER
(4)
GROUP
B
PORT
B
(8)
PA7-PA0
PC7-PC4
PC3-PC0
PB7-PB0
PA3
PA2
PA1
PA0
RD
CS
VSS
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1. 40
2. 39
3. 38
4. 37
5. 36
6. 35
7. 34
8. 33
9. 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
Figure 2
PA4
PA5
PA6
PA7
WR
Reset
D0
D1
D2
D3
D4
D5
D6
D7
VCC
PB7
PB6
PB5
PB4
PB3
1

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IN82C55 pdf, ピン配列
IN82C55A
IN82C55AN FUNCTIONAL DESCRIPTION
General
The IN82C55AN is a programmable peripheral interface device designed for use in Intel microcomputer systems. Its
function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus.
The functional configuration of the IN82C55AN is programmed by the system software so that normally no external
logic is necessary to interface peripheral devices or structures.
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface the IN82C55AN to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output instructions by the CPU. Control words and status information
are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control
Groups.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a
control word to the IN82C55AN. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that
initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control Logic, receives “control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as shown in the address decode table in the pin descriptions.
Figure 6 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will
always be a logic “1”, as this implies control word mode information.
Ports A, B, and C
The IN82C55AN contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional
characteristics by the system software but each has its own special features or “personality” to further enhance the
power and flexibility of the IN82C55AN.
Port A. One 8-bit data output latch/buffer and one 8-bit input latch/buffer. Both “pull-up” and “pull-down” bus hold
devices are present on Port A.
Port B. One 8-bit data input/output latch/buffer. Only “pull-up” bus hold devices are present on Port B.
Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided
into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control
signal outputs and status signal inputs in conjunction with ports A and B. Only “pull-up” bus hold devices are present
on Port C.
See Figure 4 for the bus-hold circuit configuration for Port A, B, and C.
3


3Pages


IN82C55 電子部品, 半導体
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
IN82C55A
Figure 6. Mode Definition Format
The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the
complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into
account things such as efficient PC board layout, control signal definition vs PC layout and complete functional
flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of
the available pins.
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. This feature reduces software
requirements in Control-based applications.
When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset
operation just as if they were data output ports.
D7 D6 D5 D4 D3 D2 D1 D0
DON’T
CARE
BIT SET/RESET
1 = SET
0 =RESET
BIT SELECT
01234567
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2
BIT SET/RESET FLAG
0 = ACTIVE
Figure 7. Bit Set/Reset Format
6

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共有リンク

Link :


部品番号部品説明メーカ
IN82C54

PROGRAMMABLE TIMER

Integral
Integral
IN82C55

Promrammable Periphral Interface

IK Semiconductor
IK Semiconductor
IN82C55AN

CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

Integral
Integral


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