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MC54HC132A PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 MC54HC132A
部品説明 Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
メーカ Motorola
ロゴ Motorola ロゴ 

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MC54HC132A Datasheet, MC54HC132A PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input NAND Gate with
Schmitt-Trigger Inputs
High–Performance Silicon–Gate CMOS
The MC54/74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 72 FETs or 18 Equivalent Gates
A1 1
LOGIC DIAGRAM
B1 2
A2 4
B2 5
A3 9
B3 10
A4 12
B4 13
PIN 14 = VCC
PIN 7 = GND
3
Y1
6
Y2
Y = AB
8
Y3
11
Y4
MC54/74HC132A
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
H
H
H
L
10/95
© Motorola, Inc. 1995
1 REV 6

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