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PDF IS1002 Data sheet ( Hoja de datos )
| Número de pieza | IS1002 | |
| Descripción | Bluetooth Baseband Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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eet4U.comIntegrated System Solution Corp.
IS1002
Bluetooth Baseband Controller
taSh1. General Description
.DaThe ISSC IS1002 is a highly integrated Bluetooth baseband controller providing capability
for high data rate, short-range wireless communications in the 2.4 GHz ISM band. It is
w fully compliant with version 1.1 of Bluetooth specification and some important BT1.2
w features. Specially engineered for low power consumption and cost effective solution, the
w ISSC IS1002 integrates a baseband controller, HCI controller, and Audio controller. It also
integrates a Turbo 8051 processor with 160K mask ROM for program memory and 32K
SRAM for data memory.
mThe ISSC IS1002 is also available with a Bluetooth compliant protocol stack, including
ohardware drivers, link manager (LM), and host controller interface (HCI).
.c2. Features
U• Compliant with Bluetooth Specification 1.1/1.2
t4• Full Bluetooth RF Interface & Lower Link Controller functions
• BlueRF Interfaces to leading Radio ICs
e• Full-featured hardware link controller with low-power mode and efficient data
movement architecture
e• Hardware support for all Bluetooth 1.1 packet types including
ho Data packets: DM1, DM3, DM5; DH1, DH3, DH5; AUX, DV
o Voice packets: HV1, HV2, HV3, DV
So Link Control packets: ID, IQ, NULL, POLL, and FHS
• Flexible and robust voice CODEC algorithms (CVSD, A-law, µ-law), with 3
tasimultaneous SCO channels support.
• Baseband functions implemented in hardware such as Forward Error Correction
a(FEC), whitening, Header Error Check (HEC), Shorten Hamming Code, CRC
generation/checking, and Encryption/De-encryption.
.D• Hardware permutation to speed up software Authentication.
• Point-to-multipoint support (Piconet).
• Scatternet support.
w• BT1.2 Adaptive Frequency Hopping (AFH) supported.
• BT1.2 Fast Connection supported.
w• Ultra-low low cost and power consumption features.
w• Integrated Turbo 8051 processor.
• Integrated 32K bytes SRAM for common data buffer.
m• Integrated 160K bytes Mask ROM for 8051 program memory.
o• HCI universal connect interface provides access to other physical host interfaces
.c(i.e. USB, UART.).
U• Full-speed UART host interface.
t4• Selectable reference clock frequencies.
e• Protocol Stack available, including drivers, link manager, and HCI.
he• 48 QFN package
www.DataSPreliminary Datasheet
page 1
Released date: July 2004
Revision 0.9
1 page  
Integrated System Solution Corp.
IS1002
Bluetooth Baseband Controller
Pin No. I/O Pin Name
44 — VDD18
45 I Battery_in
46 — VDD18O
47 — VSS_REG
48 — VDD_REG
Pin Descriptions
1.8V Vdd
Battery detection input
1.8V regulator output
Vss for regulator
Vdd for regulator
Preliminary Datasheet
page 5
Released date: July 2004
Revision 0.9
5 Page 
Integrated System Solution Corp.
IS1002
Bluetooth Baseband Controller
7.11 Processor Memory Map1
The addressable memory space of the 8051 Turbo processor consists of a 64 kByte
program space and a 64 kByte data space. The 64 kByte program space is mapped onto
two pages in a larger 128 kByte memory space. This 128 kByte space may be physically
implemented in a Flash or ROM device. The 64 kByte data space contains a single-port
RAM, and the register bank. The maximum size of each memory component is as follows.
Memory
Component
program memory
data segment 1
register segment
data segment 2
reserved
Physical
Device
Flash or ROM
Maximum
Size
128 kBytes
single port
RAM
register bank
Common
memory
32 kBytes
16 kBytes
13 kBytes
Address range
page 0: 0000h – ffffh
page 1: 0000h – ffffh
0000h – 7fffh
8000h – bfffh
c000h – f3ffh
f400h – ffffh
7.12 Miscellaneous (Watchdog Timer, PLL, and Clock Divider)
System related functions such as watchdog timer, Endian control, and interrupt vectors are
also provided.
The purpose of the watchdog timer is to provide a reset to CPU in case when the CPU
fails to service the watchdog timer in a pre-defined (programmable) period. In this
situation, the CPU will be reset, and a flag will be set to indicate that the reset was due to a
watchdog “timeout”. In addition, it also provides resets to the other modules in Bluetooth
baseband.
The build in PLL circuit will generate the required system clock of 48MHz, 36MHz or
24MHz from the oscillator clock. The clock divider will provide fixed frequencies of 12 MHz,
8KHz…for Bluetooth core and other peripheral hardware based on the input system clock
of 48MHz, 36MHz, or 24MHz. All system clocks are 50% duty cycle.
1 Additional memory spaces such as TX/RX buffer, USB/UART buffer are not addressable by 8051. Those
special memory modules are controlled indirectly by 8051 via data router.
Preliminary Datasheet
page 11
Released date: July 2004
Revision 0.9
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IS1002.PDF ] | |
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