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HIP5062 の電気的特性と機能

HIP5062のメーカーはIntersil Corporationです、この部品の機能は「Power Control IC Single Chip Dual Switching Power Supply」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP5062
部品説明 Power Control IC Single Chip Dual Switching Power Supply
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP5062 Datasheet, HIP5062 PDF,ピン配置, 機能
HIP5062
®
No ROeBcSomOLmEeTnEdePdRROeDpUlaCcTement
August 1998
File Number 3208.2
Power Control IC Single Chip Dual Switch-
ing Power Supply
The HIP5062 is a complete power control IC, incorporating
two high power DMOS transistors, CMOS logic and two low
level analog control circuits on the same Intelligent Power
IC. Both the standard “Boost” and the “SEPIC” (Single-
Ended Primary Inductance Converter) power supply
topologies are easily implemented with this single control IC.
Special power transistor current sensing circuitry is
incorporated that minimizes losses due to the monitoring
circuitry. Moreover, over-temperature and over-voltage
detection circuitry is incorporated within the IC to monitor the
chip temperature and the actual power supply output
voltage. These circuits can disable the drive to the power
transistor to protect both the transistor and, most
importantly, the load from over-voltage.
As a result of the power DMOS transistor’s current and
voltage capability (5A and 60V), multiple output power
supplies with total output power capability up to 100W are
possible.
Features
• Two Current Mode Control Regulators
• Two 60V, 5A On-chip DMOS Transistors
• Thermal Protection
• Over-Voltage Protection
• Over-Current Protection
• 1MHz Operation or External Clock
• Synchronization Output
• On-Chip Reference Voltage - 5.1V
• Output Rise and Fall Times ~ 3ns
• Designed for 26V to 42V Operation
Applications
• Single Chip Power Supplies
• Current Mode PWM Applications
• Distributed Power Supplies
• Multiple Output Converters
Ordering Information
PART NUMBER
HIP5062DY
HIP5062DW
TEMPERATURE
RANGE
0oC to +85oC
0oC to +85oC
PACKAGE
40 Pad Chip
Wafer
Chip
V+ (40)
TMON (39)
IRFI2 (38)
IRFO2 (37)
VINP (36)
AGND (35)
DGND (34)
XCKS (33)
CKIN (32)
IRFI1 (31)
IRFO1 (30)
VCMP1 (29)
VTCN (28)
(8) VDDP2
(9) VCMP2
(10) PSOK
(11) VREG2
(12) FLTN
(13) PSEN
(14) SHRT
(15) SLRN
(16) SFST
(17) VDDD
(18) VDDA
(19) VREG1
(20) VDDP1
175 mils x 175 mils (4.44mm x 4.44mm)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved

1 Page





HIP5062 pdf, ピン配列
HIP5062
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 42V
DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A
DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V
Operating Junction Temperature Range . . . . . . . . . .0oC to +110oC
Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC
Thermal Resistance
(Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . .
3oC/θWJCMax
0.050” Thick Copper Heat Sink)
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110oC
(Controlled By Thermal Shutdown Circuit)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = 0oC to +110oC; Unless Otherwise Specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
I+ Supply Current
V+ = 42V, PSEN = 12V
- 24.7 30
mA
VDDA
Internal Regulator Output
Voltage
VINP
Reference Voltage
RVINP
VINP Resistance
ERROR AMPLIFIERS
V+ = 30V to 42V, IOUT = 0mA 11.7 - 13.3
V+ = 30V to 42V, IOUT = 30mA
11.5
-
13.3
SLRN = 12V, IOUT = 0mA
11.5 - 13.3
VDDA = SLRN = 12V, IVINP = 0mA
5.01
5.1
5.19
VINP = 0
- 900 -
V
V
V
V
| VIO |
Input Offset Voltage
(REG - VINP)
IVCMP = 0mA
- - 10 mV
RIN VREG
gm (VREG)
gm (SFST)
IVCMP
Input Resistance to GND
VREG Transconductance
(IVCMP/(VREG - VINP)
SFST Transconductance
IVCMP/(VREG - SFST)
Maximum Source Current
Maximum Sink Current
VREG = 5.1V
39 - 85
VCMP = 1V to 8V, SFST = 11V
15
30
50
k
mS
VSFST < 4.9V
VREG = 4.95V, VCMP = 8V
VREG = 5.25V, VCMP = 0.4V
0.8
-2.5
0.75
- 6 mS
-
-0.75
mA
- 2.5 mA
OVTH
Over-Voltage Threshold
Voltage at VREG for FLTN to be
latched
6.05
-
6.5
V
CLOCK
fq
VTH CKIN
Internal Clock Frequency
External Clock Input Threshold
Voltages
XCKS = 12V, VDDD = 12V
0.9 1.0 1.1 MHz
33 - 66 %VDDD
DMOS TRANSISTORS
rDS(on)
Drain-Source On-State
Resistance
I Drain = 2.5A,
TJ = +25oC
VDDD
=
11V,
-
- 0.22
IDSS
Drain-Source Leakage Current Drain to Source Voltage = 60V
-
1 100 µA
CURRENT CONTROLED PWM
|VIO| VCMP
Buffer Offset Voltage (VCOMP -
VIFRO)
IFRO = 0mA to -5mA,
VTCN = 0.2V to 7.6V,
VCMP2 = 0.2V to 7.6V
- - 125 mV
3


3Pages


HIP5062 電子部品, 半導体
HIP5062
Pin Descriptions (Continued)
PAD NUMBER DESIGNATION
DESCRIPTION
32
CKIN
Clock input when XCKS is grounded.
33
XCKS
Grounding this terminal provides for the application of an external clock to CKIN input terminal.
For normal internal clock operation, this terminal may be left floating or returned to 12V. There
is an internal 30K pull-up resistor on this terminal.
34
DGND
Ground of the DMOS gate drivers. This pad is used for bypassing.
35
AGND
Analog ground.
36
VINP
Internal 5.1V reference. This point is usually bypassed.
37
IRFO2
A resistor placed between this pad and IRFI2 converts the VCMP2 signal to a current for the cur-
rent sense comparator. The maximum current set by the value of the resistor, according to the
equation: IPEAK = 16/R. Where R is the value of the external resistor in Kand must be greater
than 1.5Kbut less than 10K. For example, if the resistor chosen is 1.8K, the peak current will
be 8.8A. This assumes VCMP2 is 7.3V. Maximum output current should be kept below 10A.
38
IRFI2
See IRFO2.
39
TMON
This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to VDDA or 12V the function is disabled. Returning this pad to ground will put
the IC into the thermal shutdown state. Thermal shutdown occurs at a nominal junction temper-
ature or +120oC. This terminal is normally returned to ground.
40 V+ This is the main supply voltage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.1µF capacitor.
6

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