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EP20K60Exxxx の電気的特性と機能

EP20K60ExxxxのメーカーはAlteraです、この部品の機能は「(APEP20K Series) Programmable Logic Device Family」です。


製品の詳細 ( Datasheet PDF )

部品番号 EP20K60Exxxx
部品説明 (APEP20K Series) Programmable Logic Device Family
メーカ Altera
ロゴ Altera ロゴ 




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EP20K60Exxxx Datasheet, EP20K60Exxxx PDF,ピン配置, 機能
March 2004, ver. 5.1
APEX 20K
Programmable Logic
Device Family
Data Sheet
Features
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
– MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
– LUT logic used for register-intensive functions
– Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
– ESB implementation of product-term logic used for
combinatorial-intensive functions
High density
– 30,000 to 1.5 million typical gates (see Tables 1 and 2)
– Up to 51,840 logic elements (LEs)
– Up to 442,368 RAM bits that can be used without reducing
available logic
– Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features Note (1)
Feature
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
EP20K30E EP20K60E
113,000 162,000
30,000
1,200
12
24,576
192
128
60,000
2,560
16
32,768
256
196
EP20K100
263,000
100,000
4,160
26
53,248
416
252
EP20K100E EP20K160E
263,000
404,000
100,000
4,160
26
53,248
416
246
160,000
6,400
40
81,920
640
316
EP20K200
526,000
200,000
8,320
52
106,496
832
382
EP20K200E
526,000
200,000
8,320
52
106,496
832
376
Altera Corporation
DS-APEX20K-5.1
1

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EP20K60Exxxx pdf, ピン配列
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
– Built-in low-skew clock tree
– Up to eight global clock signals
– ClockLock® feature reducing clock delay and skew
– ClockBoost® feature providing clock multiplication and division
– ClockShiftTM programmable clock phase and delay shifting
Powerful I/O features
– Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
– Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
– Bidirectional I/O performance (tCO + tSU) up to 250 MHz
– LVDS performance up to 840 Mbits per channel
– Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
– MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
– Programmable clamp to VCCIO
– Individual tri-state output enable control for each pin
– Programmable output slew-rate control to reduce switching
noise
– Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
– Pull-up on I/O pins before and during configuration
Advanced interconnect structure
– Four-level hierarchical FastTrack® Interconnect structure
providing fast, predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
– Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
Advanced packaging options
– Available in a variety of packages with 144 to 1,020 pins (see
Tables 4 through 7)
– FineLine BGA® packages maximize board space efficiency
Advanced software support
– Software design support and automatic place-and-route
provided by the Altera® Quartus® II development system for
3


3Pages


EP20K60Exxxx 電子部品, 半導体
APEX 20K Programmable Logic Device Family Data Sheet
General
Description
APEXTM 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and product-
term-based devices with an enhanced memory structure. LUT-based logic
provides optimized performance and efficiency for data-path, register-
intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines. LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K device architecture uniquely suited
for system-on-a-programmable-chip designs. Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
APEX 20KE devices are a superset of APEX 20K devices and include
additional features such as advanced I/O standard support, CAM,
additional global clocks, and enhanced ClockLock clock circuitry. In
addition, APEX 20KE devices extend the APEX 20K family to 1.5 million
gates. APEX 20KE devices are denoted with an “E” suffix in the device
name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8
compares the features included in APEX 20K and APEX 20KE devices.
6 Altera Corporation

6 Page



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共有リンク

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部品番号部品説明メーカ
EP20K60Exxxx

(APEP20K Series) Programmable Logic Device Family

Altera
Altera
EP20K60Exxxx

(EP20KxxxE) Programmable Logic Device Family

Altera Corporation
Altera Corporation


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