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PDF IRM7001 Data sheet ( Hoja de datos )
| Número de pieza | IRM7001 | |
| Descripción | SIR Modulator/Demodulator | |
| Fabricantes | Vishay Siliconix | |
| Logotipo |  |
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IRM7001
SIR Modulator/Demodulator
FEATURES
• Compliant with IrDA 1.0 Physical Layer Specifications
• Interfaces with IrDA 1.0 Compliant IR Transceivers
• Used in conjunction with Standard 16550 UART
• Transmits/Receives either 1.6µs or 3/16 Pulse Mode
• Internal or External Clock Mode
• Programmable Baud Rate
• 2.7–5.5 V Operation
• 16 Pin SOIC Package
APPLICATIONS
• Interfaces with IR Transceivers in:
- Computer Applications:
PDAs
Dongle or other RS232 Adapter
- Telecom Application:
Modems
Fax Machines
Pagers
- Handheld Data Collection:
Industrial
Medical
Transportation
DESCRIPTION
The IRM7001 SIR-Encoder/Decoder is a CMOS modulator/
demodulator chip that is used to both encode and decode
information as per the IrDA® SIR (Serial InfraRed) signal mod-
ulation and demodulation scheme. This chip is designed to
work with Infineon IrDA compatible transceivers and all other
IrDA compatible transceivers. The chip contains a clock
divider circuit used to generate the 16X clock internally. This
makes it very suitable for microcontroller-based embedded
system design.
Dimensions in inches (mm)
A.393 (10.0)
.386 (9.8)
SOIC Package
16 9 B
.157 (4.0) .244 (6.2)
1 8 .150 (3.8) .229 (5.8)
.050 (1.27) BSC .068 (1.75)
.054 (1.35)
R x 45°
.009 (.25)
.008 (.19)
T
.019 (.49)
.014 (.35)
.009 (.25)
.004 (0.1)
.049 (1.25)
7° .016 (.40)
Notes:
1. Dimensions A and B are datums and T is a datum surface.
2. Dimensioning and tolerancing per ansi Y14.5M, 1982
3. Controlling dimension: millimeter.
4. Dimension A and B do not include mold protrusion.
5. Maximum mold protrusion 0.15 (0.005) per side.
Figure 1. IRM7001 pin out
IRM - 7001
16XCLK
TXD
RCV
A0
A1
A2
CLK_SEL
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
OSCIN
OSCOUT
PWR DN
PLS MOD
IR_TXD
IR_RCV
NRST
Figure 2. IRM7001 Block Diagram
TXD
/NRST
RCV
A0
A1
A2
16XCLK
PULSEMOD
CLK_SEL
SIR
ENCODE
IR_TXD
SIR
DECODE
IR_RCV
INT_CLOCK
CLOCK
DIVIDE
Document Number: 82576
Revision 17-August-01
www.vishay.com
1
1 page  
Table 5. Operating Conditions at VCC=2.7 V
Parameter
Symbol
Supply voltage
Input voltage
Ambient temperature
VCC
VIN
Ta
High-Level Input Voltage
Low-Level Input Voltage
Output High Voltage
Output Low Voltage
Static Power Dissipation
Dynamic Power Dissipation
Static Current Consumption
Dynamic Power Dissipation
Max Clk Frequency(16XCLK)
Minimum Pulse Width(IR_TXD)
Pulse Width on monoshot (IR_TXD)
Output Capacitance on Output Pads
used for simulation
VIH
VIL
VOH
VOL
PSTAT
PDYN
ISTAT
IDYN
f16xclk
tmpw
tmpw
COUT
Value of pulldown resistor used on
RDWN
POWERDN & PULSEMOD input pins
Trigger Low Level Input Voltage
(For /NRST input pin)
VIL_TRIG
Trigger High Level Input Voltage
(For /NRST input pin)
VIH_TRIG
Min
2.7
0
–20
0.7 VCC
0
2.2
1630
1630
114
0.7
1.7
Typ
5
0.11
5.4
40
2
1710
152
0.8
1.85
Max
5.5
VCC
+85
VCC
0.3 VCC
0.5
0.15
8.1
54
3
2
1730
50
256
0.9
1.9
Unit
V
V
°C
V
V
V
V
mW
mW
µA
mA
MHz
ns
ns
pF
KOhms
V
V
Conditions
IOH=2.0 mA
IOL=2.0 mA
Document Number: 82576
Revision 17-August-01
www.vishay.com
5
5 Page 
Design Notes:
1. When internal is used, CLK_SEL should be held low (con-
nected to GND). In case of external clock CLK_SEL should
be tied high (VCC).
2. If PULSEMOD is held high and the internal clock is used, the
IR_TXD is limited to a duration of 1.6µs irrespective of data
rate. This helps in reducing LED current at lower data rates.
This function cannot be used with external clock (16XCLK).
3. There are two methods of putting the internal oscillator cell in
POWERDN MODE. Firstly, whenever CLKSEL line is
asserted high, the oscillator cell is automatically put in
power down mode. Secondly, the user may also decide to
put the oscillator in power down mode by providing a high
signal on the POWERDN input pin. Normally the POWERDN
pin stays low.
PACKAGING
Production Package
The package is SOIC 16 pins (150 mils) plastic package.
Chips will be available in Tape and Reel (2500 units per reel).
QUALITY AND RELIABILITY
E.S.D. and latch-up
Maximum DC current through any pin thus avoiding latch-up:
+/- 100 mA Electrostatic discharge protection: 4000 V for
mono-supply voltage Electrostatic discharge protection: 2000
V for multi-supplies voltages E.S.D. sensitivity: MIL STD-883-
3015.7 Class 2
Specific requirements: environmental endurance
A. Permanence of marking: MIL-STD-883 - Method 2015
B. Solderability: MIL-STD-883 - Method 2003
C. Resistance to soldering heat: MIL-STD-883 - Method 200
Document Number: 82576
Revision 17-August-01
www.vishay.com
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet IRM7001.PDF ] | |
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