|
|
PDF MX10EXA Data sheet ( Hoja de datos )
| Número de pieza | MX10EXA | |
| Descripción | XA 16-bit Microcontroller Family 64K Flash/2K RAM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MX10EXA (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
FEATURE
PRELIMINARY
MX10EXA
XA 16-bit Microcontroller Family
64K Flash/2K RAM, Watchdog, 2UARTs
• 4.5V to 5.5V
• 64K bytes of on-chip Flash program memory with In-
System Programming capability
• Five Flash blocks = two 8k byte blocks and three 16k
byte blocks
• Single supply voltage In-System Programming of the
Flash memory, (VPP=VDD or VPP=12V ifdesired)
• Boot ROM contains low level Flash programming
routines for In-Application Programming and a default
serial loader using the UART
• 2048 bytes of on-chip data RAM
• Supports off-chip program and data addressing up to 1
megabyte (20 address lines)
• Three standard counter/timers with enhanced features
All timers have a toggle output capability
• Watchdog timer
• Two enhanced UARTs with independent baud rates
• Seven software interrupts
• Four 8-bit I/O ports, with 4 programmable output
configurations for each pin
• 30 MHz operating frequency at 5V
• Power saving operating modes: Idle and Power-
Down.Wake-Up from power-down via an external inter-
rupt is supported.
• 44-pin PLCC (MX10EXAQC) and 44-pin LQFP
(MX10EXAUC) packages
GENERAL DESCRIPTION
The MX10EXA is a member of Philips’ 80C51 XA
(eXtended Architecture) family of high performance 16-
bit single-chip microcontrollers.
The MX10EXA contains 64k bytes of Flash program
memory, and provides three general purpose timers/
counters, a watchdog timer, dual UARTs, and four gen-
eral purpose I/O ports with programmable output con-
figurations.
A default serial loader program in the Boot ROM allows
In-System Programming (ISP) of the Flash memory with-
out the need for a loader in the Flash code. User pro-
grams may erase and reprogram the Flash memory at
will through the use of standard routines contained in
the Boot ROM (In-Application Programming).
PIN CONFIGURATIONS
44 PLCC
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
6
7
12
17
18
1 44
MX10EXAQC
23
40
39 P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
34 NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
29 P2.5/A17D13
28
44 LQFP
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
44
1
11
12
MX10EXAUC
34
33 P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
23 P2.5/A17D13
22
P/N:PM0625
REV. 1.1, MAY 05, 1999
1
1 page  
MX10EXA
SPECIAL FUNCTION REGISTERS
NAME
AUXR
BCR
BTRH
BTRL
CS
DS
ES
IEH*
IEL*
IPA0
IPA1
IPA2
IPA4
IPA5
P0*
P1*
P2*
P3*
DESCRIPTION
SFR BIT FUNCTIONS AND ADDRESSES
Reset
ADDRESS MSB
LSB VALUE
Auxiliary function register 44C ENBOOT FMIDLE PWR_VLD ---
--- ---
--- ---
Bus configuration register 46A——— --- ---
--- WAITD BUSD BC2 BC1 BC0 Note 1
Bus timing register high byte 469 DW1 DW0 DWA1 DWA0 DR1 DR0 DRA1 DRA0 FF
Bus timing register low byte 468 WM1 WM0 ALEW — --- CR1 CR0 CRA1 CRA0 EF
Code segment
443
00
Data segment
441
00
Extra segment
442
00
33F 33E 33D 33C 33B 33A 339 338
Interrupt enable high byte 427 --- ---
---
--- ETI1 ERI1 ETI0 ERI0 00
337 336 335 334 333 332 331 330
Interrupt enable low byte 426 EA --- ---
ET2 ET1 EX1 ET0 EX0 00
Interrupt priority 0
4A0 ---
PT0
--- PX0 00
Interrupt priority 1 4A1 --- PT1 --- PX1 00
Interrupt priority 2
4A2 ---
---
--- PT2 00
Interrupt priority 4
4A4 ---
PTI0
---
PRI0
00
Interrupt priority 5
4A5 ---
PTI1
---
PRI1
00
387 386 385 384 383 382 381 380
Port 0
430 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FF
38F 38E 38D 38C 38B 38A 389 388
Port 1
431 T2EX T2 TxD1 RxD1 A3 A2 A1 WRH FF
397 396 395 394 393 392 391 390
Port 2
432 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 FF
39F 39E 39D 39C 39B 39A 399 398
Port 3
433 RD WR T1 T0 INT1 INT0 TxD0 RxD0 FF
P0CFGA Port 0 configuration A
P1CFGA Port 1 configuration A
P2CFGA Port 2 configuration A
P3CFGA Port 3 configuration A
P0CFGB Port 0 configuration B
P1CFGB Port 1 configuration B
P2CFGB Port 2 configuration B
P3CFGB Port 3 configuration B
P/N:PM0625
470
471
472
473
4F0
4F1
4F2
4F3
5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
REV. 1.1, MAY 05, 1999
5 Page 
MX10EXA
CAPABILITIES OF THE PHILIPS 89C51 FLASH-
BASED MICROCONTROLLERS
Flash organization
The XA contains 64k bytes of Flash program memory.
This memory is organized as 5 separate blocks. The
first two blocks are 8k bytes in size, filling the program
memory space from address 0 through 3FFF hex. The
final three blocks are 16k bytes in size and occupy ad-
dresses from 4000 through FFFF hex.
Figure 3 depicts the Flash memory configuration.
Flash Programming and Erasure
The XA Flash microcontroller supports a number of pro-
gramming possibilities for the on-chip Flash memory.The
Flash memory may be programmed in a parallel fashion
on standard programming equipment in a manner similar
to an EPROM microcontroller.The XA microcontroller is
able to program its own Flash memory while the applica-
tion code is running. Also, a default loader built into a
Boot ROM allows programming blank devices serially
through the UART.
Using any of these types of programming, any of the
individual blocks may be erased separately, or the entire
chip may be erased. Programming of the Flash memory
is accomplished one byte at a time.
Boot ROM
When the microcontroller programs its own Flash
memory, all of the low level details are handled by code
that is permanently contained in a 2k byte “Boot ROM”
that is separate from the Flash memory. A user program
simply calls the entry point with the appropriate
parameters to accomplish the desired operation. Boot
ROM operations include things like: erase block, program
byte, verity byte, program security lock bit, etc.The Boot
ROM overlays the program memory space at the top of
the address space from F800 to FFFF hex, when it is
enabled by setting the ENBOOT bit at AUXR1.7.. The
Boot ROM may be turned off so that the upper 2k bytes
of Flash program memory are accessible for execution.
ENBOOT and PWR_VLD
Setting the ENBOOT bit in the AUXR register enables
the Boot ROM and activates the on-chip VPP generator if
VPP is connected to rather than 12V externally. The
PWR_VLD flag indicates that VPP is available for
programming and erase operations. This flag should be
checked prior to calling the Boot ROM for programming
and erase services. When ENBOOT is set, it typically
takes 5 microseconds for the internal programming
voltage to be ready.
The ENBOOT bit will automatically be set if the status
byte is non-zero during reset, or when PSEN is low, ALE
is high, and EA is high at the falling edge of reset. Other-
wise, ENBOOT will be cleared during reset.
When programming functions are not needed, ENBOOT
may be cleared. This enables access to the 2k bytes of
Flash code memory that is overlaid by the Boot ROM,
allowing a full 64k bytes of Flash cede memory.
FFFF
BLOCK 4
16K BYTES
BOOT ROM
FFFF
F800
C000
PROGRAM 8000
ADDRESS
4000
2000
0000
BLOCK 3
16K BYTES
BLOCK 2
16K BYTES
BLOCK 1
8K BYTES
BLOCK 0
8K BYTES
Figure 3. Flash Memory Configuration
P/N:PM0625
REV. 1.1, MAY 05, 1999
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX10EXA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MX10EXA | XA 16-bit Microcontroller Family 64K Flash/2K RAM | Macronix International |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |