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PDF HM5165805F Data sheet ( Hoja de datos )
| Número de pieza | HM5165805F | |
| Descripción | (HM5164805F / HM5165805F) 64 MEDO DRAM (8-Mword X 8-bit) 8 k Refresh/4 k Refresh | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HM5164805F Series
HM5165805F Series
64 M EDO DRAM (8-Mword × 8-bit)
8 k Refresh/4 k Refresh
ADE-203-1057B (Z)
Rev. 2.0
Nov. 30, 1999
Description
The Hitachi HM5164805F Series, HM5165805F Series are 64M-bit dynamic RAMs organized as
8,388,608-word × 8-bit. They have realized high performance and low power by employing CMOS process
technology. HM5164805F Series, HM5165805F Series offer Extended Data Out (EDO) Page Mode as a
high speed access mode. They have the package variation of standard 32-pin plastic SOJ and standard 32-
pin plastic TSOPII.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 50 ns/60 ns (max)
• Power dissipation
Active: 414 mW/378 mW (max) (HM5164805F Series)
: 486 mW/414 mW (max) (HM5165805F Series)
Standby : 1.8 mW (max) (CMOS interface)
: 1.1 mW (max) (L-version)
• EDO page mode capability
• Refresh cycles
RAS-only refresh
8192 cycles /64 ms (HM5164805F, HM5164805FL)
4096 cycles /64 ms (HM5165805F, HM5165805FL)
CBR/Hidden refresh
4096 cycles /64 ms (HM5164805F, HM5164805FL, HM5165805F, HM5165805FL)
1 page  
HM5164805F Series, HM5165805F Series
Block Diagram (HM5164805F Series)
RAS
CAS
WE
OE
Timing and control
A0
A1 Column
• address
to •
• buffers
A9
•
•
• Row
address
buffers
A10
to
A12
Column decoder
8M array
8M array
8M array
8M array
8M array
8M array
8M array
8M array
I/O buffers
I/O0
to
I/O7
5
5 Page 
HM5164805F Series, HM5165805F Series
AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *19
Test Conditions
• Input rise and fall time: 2 ns
• Input pulse levels: VIL = 0 V, VIH = 3.0 V
• Input timing reference levels: 0.8 V, 2.0 V
• Output timing reference levels: 0.8 V, 2.0 V
• Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
Parameter
Random read or write cycle time
RAS precharge time
CAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
CAS hold time
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
Symbol
t RC
t RP
t CP
t RAS
t CAS
t ASR
t RAH
t ASC
t CAH
t RCD
t RAD
t RSH
t CSH
t CRP
t OED
t DZO
t DZC
tT
HM5164805F/HM5165805F
-5 -6
Min Max Min Max Unit
84 — 104 — ns
30 — 40 — ns
8 — 10 — ns
50 10000 60 10000 ns
8
10000 10
10000 ns
0 — 0 — ns
8 — 10 — ns
0 — 0 — ns
8 — 10 — ns
12 37 14 45 ns
10 25 12 30 ns
13 — 15 — ns
35 — 40 — ns
5 — 5 — ns
13 — 15 — ns
0 — 0 — ns
0 — 0 — ns
2 50 2 50 ns
Notes
3
4
5
6
6
7
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HM5165805F.PDF ] | |
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