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UPD765B の電気的特性と機能

UPD765BのメーカーはNEC Electronicsです、この部品の機能は「Single / Double Density Floppy-Disk Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD765B
部品説明 Single / Double Density Floppy-Disk Controller
メーカ NEC Electronics
ロゴ NEC Electronics ロゴ 




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UPD765B Datasheet, UPD765B PDF,ピン配置, 機能
NEC
NEC Electronics Inc.
uPD765A/uPD765B
Single/Double Density
Floppy-Disk Controller
Description
The uPD765A/B is an LSI floppy disk controller (FDC)
chip which contains the circuitry and control functions
for interfacing a processor to 4 floppy disk drives. It is
capableof either IBM 3740singledensity format (FM), or
IBM System 34 double density format (MFM) including
double-sided recording. The uPD765A/B provides con-
trol signals which simplify the design of an external
phase-locked loop and write precompensation circuitry.
The FDC simplifies and handles most of the burdens as-
sociated with implementing a floppy disk interface.
Hand-shaking signals are provided in the uPD765A/B
which make DMA operation easy to incorporate with the
aid of an external DMA controller chip, such as the
uPD8257. The FDC will operate in eitherthe DMA or non-
DMA mode. In the non-DMA mode the FDC generates
interrupts to !he processor every time a data byte is to
be transferred. In the DMA mode, the processor need
only load the command into the FDC and all data
transfers occur under control of the FDC and DMA
controllers.
There are 16 commands which the uPD765A/uPD765B
will execute. Most of these commands require multiple
8-bit bytes to fully specify the operation which the
processor wishes the FDC to perform. The following
commands are available.
Read Data
Read ID
Specify
Read Diagnostic
Scan Equal
Scan High or Equal
Scan Low or Equal
Version
Read Deleted Data
Write Data
Write ID (Format Write)
Write Deleted Data
Seek
Recalibrate
Sense Interrupt Status
Sense Drive Status.
Ordering Information
Device Number
uPD765AC2
uPD765B
Package Type
40-pin plastic DIP
40-pin plastic DIP
Max Freq. of Operation
8 MHz
8 MHz
Features
Address mark detection circuitry is internal to the FDC
which simplifies the phase-locked loop and read elec-
tronics. The track stepping rate, head load time, and
head unload time are user-programmable. The
uPD765A/uPD765B
offers additional features such as
multi-track and multi-side read and write commands
and single and double density capabilities.
FM, MFM Control
Variable recording length: 128,256, .8192 bytes/
sector
IBM-compatible format (single- and double-
sided, single- and double-density)
Multi-sector and multi-track transfer capability
Drive up to 4 floppy or micro floppydisk drives
Data scan capability-will scan a single sector or
an entire cylinder comparing byte-for-byte host
memory and disk data
Data transfers in DMA or non-DMA mode
Parallel seek operations on up to four drives
Compatible with uPD8080/85, uPD8086/88,
and uPD780 (Z80@) microprocessors
V-series
Single-phase clock: 8 MHz maximum
3 +5V only
Z80 is a registered trademark of the Zilog Corporation
Pin Configuration
NECEL-000324
5-3

1 Page





UPD765B pdf, ピン配列
NEC
uPD765A/uPD765B
WCLK (Write Clock)
The WCLK input sets the data write rate to the FDD. It is
500 kHz for FM, 1 MHz for MFM drives, for 8 MHz opera-
tion of the FDC; 250kHz FM or 500 kHz MFM for 4 MHz
FDC operation.
This signal must be input for read and write cycles
WCLK’s rising edge must be synchronized with CLK’s
rising edge, except for the uPD765B.
WINDOW (Read Data Window)
The WINDOW input is generated by the phase-locked
loop (PLL). It is used to sample data from the FDD and in
distinguishing between clock and data bits in the FDC.
RDATA (Read Data)
The RDATA input is the read data from the FDD,
containing clock and data bits. To avoid a deadlock
situation, input RDATA and WINDOW together.
WDATA (Write Data)
WDATA is the serial clock and data output to the FDD.
WE (Write Enable)
The WE output enables write data into the FDD.
SYNC (VCO Sync)
The SYNC output inhibits the VCO in the PLL when low,
enables it when high.
MFM (MFM Mode)
The MFM output shows the VCO’s operation mode. It is
high for MFM, low for FM.
SIDE (Head Select)
Head 1 is selected when the SIDE output is 1 (high), head
0 is selected when SIDE is 0 (low).
U S 0 US1 (Unit Select 0,1)
The US0 and US1 outputs select up to 4 floppy disk drive
units using an external decoder.
PS0, PS1 (Preshift 0,1)
The PS0 and PS1 outputs are the write precompensation
request signals for MFM mode. They determine early,
late, and normal times for WDATA shifting.
READY (Ready)
The READY input indicates that the FDD is ready to re-
ceive data.
HDLD (Head Load)
The HDLD output is the command which causes the
read/write head in the FDD to contact the diskette.
FLT/TRKO (Fault/Track 0)
In the read/write mode, the FLT input detects FDD fault
conditions. In the seek mode, TRKO indicates track 0
head position.
WPRT/2SlDE (Write Protect/Two Side)
In the read/write mode, the WPRT input senses write
protected status (at the drive or media.) In the seek
mode, 2SIDE senses two-sided media.
FLTR/STEP (Fault Reset/Step)
In the read/write mode, the FLTR output resets the fault
flip-flop in the FDD. In the seek mode, STEP outputs
step pulses to move the head to another cylinder. A fault
reset pulse is issued at the beginning or each Read or
Write command prior to the HDLD signal.
LCT/DlR (Low Current/Direction)
In the read/write mode, the LCT output indicates that
the R/W head is positioned at cylinder 42 or greater. In
the seek mode, the DIR output determines the direction
the head will move in when it receives a step pulse. If
DIR is 0, seeks are performed in the outward direction;
DIR is 1, seeks are performed in the inward direction.
RWlSEEK (Read/Write/Seek)
The RW/SEEK output specifies the read/write mode
when low, and the seek mode when high.
GND (Ground)
Ground.
Vcc(+5v)
+5 V power supply.
5-5


3Pages


UPD765B 電子部品, 半導体
uPD765AIuPD7656
AC Characteristics
= -10 to
=V
Parameter
Symbol Min Typ
Clock period
120 125
240 250
Clock active
(high, low)
40
Clock rise
time
Clock fall
time
--
DACK
setup time to RO
--
CS, DACK
hold time from
0
0
width
200
Data access
from
DB to float delay
time from
--
CS. OACK
setup time to WR I
AW
10
0
OACK
hold time
0
width
200
Data setup time to
100
Max Unit Conditions
500 C L K
ns CLK
20
20 ns
ns
140
85 ns
= 100
ns
ns
ns
Data hold time from
0
ns
time from
INT delay time from
ns Non-DMA
+
+ 135
mode
+ 135
cycle time
13
ns (Note 4)
DACK
delav
140 ns
DRQ DACK
delay
200 n s
ns (Note 4)
DACK width
AA
+ 15
ns
TC width
1
Reset width
14
DRQ INT
response time
60 7 7
only
INT DACK
ineffective
1
Parameter
WCLK cycle time
Symbol
WCLK active time
CLK
delay
WCLK
WCLK. RDATA and
WINDOW time
WCLK,
and
WINDOW fall time
Preshift
time
from WCLK
WCLK
delav
RDATA
time
Window cycle time
Window hold time
from RDATA
Window setup time
to RDATA
setup time
to SEEK
SEEK setup time
to DIR
Direction setup time
to step
hold time
from step t
Step active time
(high)
Step cycle time
Fault reset
time (high)
Write data width
hold time
after seek
SEEK hold time
from DIR
DIR hold time
after step
Index pulse
Min Typ
16
8
250
Max
350
Conditions
MFM = 0
MFM = 1
ns Note 4
0 ns
only
20 ns
20 ns
20 ns
2 0 100 ns
2 0 100 ns
40 n s
2
1
15
MFM=O
ns
15 n s
12 CLK
Notes 4, 5
7
5.0
678
33 Note 2Note 2
8.0 10
Notes 4.5
15 CLK
Notes 3.4.
5
30 CLK
Notes 4, 5
24
4

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD765

SINGLE/DOUBLE DENSITY FLOPPY DISK CONTROLLER

NEC
NEC
UPD765A

Single / Double Density Floppy-Disk Controller

NEC Electronics
NEC Electronics
UPD765B

Single / Double Density Floppy-Disk Controller

NEC Electronics
NEC Electronics


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