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PDF ISPLSI2032 Data sheet ( Hoja de datos )
| Número de pieza | ISPLSI2032 | |
| Descripción | (ISPLSI2032/A) In-System Programmable SuperFAST High Density PLD | |
| Fabricantes | Lattice Semiconductor | |
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ispLSI® 2032/A
In-System Programmable High Density PLD
Features
• ENHANCEMENTS
— ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
— ispLSI 2032A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Functional Block Diagram
A0
Global Routing Pool
(GRP)
A1
A2 GLB
A3
DQ
DQ
Logic
Array D Q
DQ
A7
A6
A5
A4
Description
0139Bisp/2000
The ispLSI 2032 and 2032A are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
2032_10
1
1 page  
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 4
COND.
#2
DESCRIPTION1
-180
-150
-135
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 5.0 – 5.5 – 7.5 ns
tpd2
A 2 Data Prop. Delay
– 7.5 – 8.0 – 10.0 ns
fmax
A 3 Clk Frequency with Internal Feedback 3
180 – 154 – 137 – MHz
fmax (Ext.)
fmax (Tog.)
–
4
Clk Frequency with Ext. Feedback
( )1
tsu2 + tco1
125
–
111
–
100
–
MHz
– 5 Clk Frequency, Max. Toggle
200 – 167 – 167 – MHz
tsu1
– 6 GLB Reg Setup Time before Clk, 4 PT Bypass 3.0 – 3.0 – 4.0 – ns
tco1
A 7 GLB Reg. Clk to Output Delay, ORP Bypass
– 4.0 – 4.5 – 4.5 ns
th1 – 8 GLB Reg. Hold Time after Clk, 4 PT Bypass 0.0 – 0.0 – 0.0 – ns
tsu2
– 9 GLB Reg. Setup Time before Clk
4.0 – 4.5 – 5.5 – ns
tco2
– 10 GLB Reg. Clk to Output Delay
– 4.5 – 5.0 – 5.5 ns
th2 – 11 GLB Reg. Hold Time after Clk
0.0 – 0.0 – 0.0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay
– 7.0 – 8.0 – 10.0 ns
trw1
– 13 Ext. Reset Pulse Duration
4.0 – 4.5 – 5.0 – ns
tptoeen
B 14 Input to Output Enable
– 10.0 – 11.0 – 12.0 ns
tptoedis
C 15 Input to Output Disable
– 10.0 – 11.0 – 12.0 ns
tgoeen
B 16 Global OE Output Enable
– 5.0 – 5.0 – 6.0 ns
tgoedis
C 17 Global OE Output Disable
– 5.0 – 5.0 – 6.0 ns
twh
– 18 Ext. Synchronous Clk Pulse Duration, High
2.5 – 3.0 – 3.0 – ns
twl
– 19 Ext. Synchronous Clk Pulse Duration, Low
2.5 – 3.0 – 3.0 – ns
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B-180/2032
5
5 Page 
Specifications ispLSI 2032/A
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
44-PIN PLCC
PIN NUMBERS
15, 16, 17, 18,
19, 20, 21, 22,
25, 26, 27, 28,
29, 30, 31, 32,
37, 38, 39, 40,
41, 42, 43, 44,
3, 4, 5, 6,
7, 8, 9, 10
44-PIN TQFP
PIN NUMBERS
9, 10, 11, 12,
13, 14, 15, 16,
19, 20, 21, 22,
23, 24, 25, 26,
31 32, 33, 34,
35, 36, 37, 38,
41, 42, 43, 44,
1, 2, 3, 4
48-PIN TQFP
PIN NUMBERS
9, 10, 11, 13,
14, 15, 16, 17,
20, 21, 22, 23,
25, 26, 27, 28,
33, 34, 35, 37,
38, 39, 40, 41,
44, 45, 46, 47,
1, 2, 3, 4
DESCRIPTION
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
GOE 0
2
40 43 Global Output Enable input pin.
Y0 11 5 5 Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
RESET/Y1
35
29
31 This pin performs two functions:
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
ispEN
SDI/IN 02
13
14
7
8
7 Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and SCLK
controls become active.
8 Input — This pin performs two functions. When ispEN
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
When ispEN is high, it functions as a dedicated input
pin.
MODE
SDO/IN 12
SCLK/Y22
36
24
33
GND
1, 23
30
18
27
17, 39
32
19
29
18, 42
Input — When in ISP Mode, controls operation of ISP
state machine.
Output/Input — This pin performs two functions. When
ispEN is logic low, it functions as an output pin to read
serial shift register data. When ispEN is high, it
functions as a dedicated input pin.
Input — This pin performs two functions. When
ispEN is logic low, it functions as a clock pin for the
Serial Shift Register. When ispEN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
Ground (GND)
VCC
NC1
12, 34
6, 28
6, 30
VCC
12, 24, 36, 48 No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Table 2-0002A-08isp/2032
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISPLSI2032.PDF ] | |
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