PDF PNX8526 Data sheet ( Hoja de datos )

Número de pieza	PNX8526
Descripción	Programmable source decoder with integrated peripherals
Fabricantes	NXP Semiconductors
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No Preview Available ! PNX8526 Programmable source decoder with integrated peripherials Rev. 02 — 11 July 2005 Product data sheet 1. General description The PNX8526 is a highly integrated media processor for use in Advanced Set Top Boxes (ASTB) and Digital Television (DTV) systems. The PNX8526 is targeted at the mid to high-end ASTB/DTV systems, decoding ‘all format’ HD and SD MPEG-2 source material with Standard Deﬁnition (SD), or double line-rate SD display capabilities. Although the PNX8526 can process high level input formats, its display capabilities are primarily targeted at NTSC, PAL and SECAM televisions. It is also intended for lower cost DTVs, those not considered high deﬁnition. Progressive output is also available for double line-rate television displays, or for high resolution graphic content to be displayed on a computer monitor. The PNX8526 is designed in a high performance 0.12 micron process. The PNX8526 performs source decode functions, including conditional access, MPEG-2 transport stream demultiplexing, MPEG-2 video decode, audio decode and processing, graphics generation, video processing, and image composition and display. A 32-bit, 200 MHz VLIW processor, referred to as the TriMedia 3200 CPU core (TM32 CPU), carries out the majority of media processing operations performed by the PNX8526. Fixed function hardware will perform some operations that are not handled by the TM32 CPU. Additionally, the PNX8526 supports a number of peripheral interfaces such as I2C-bus, USB, IDE and UART. Other interfaces such as IEEE-1284 and Ethernet may be supported via SuperI/O devices that reside on a PCI expansion bus. The expansion bus also provides for glueless interface to 8-bit wide slave devices, such as ﬂash/ROM, DOCSIS modem, UARTs, etc. An embedded MIPS processor (PR3940) running at 150 MHz is intended to run the OS. (There is no direct support for an external processor; however, a CPU of any type may be connected to the PNX8526 via the PCI interface.) This implies a complete CPU subsystem consisting of the CPU itself, local memory, and an interface to PCI. The MIPS processor is primarily responsible for control functions and graphics-intensive operating systems, while the TM32 CPU is responsible for running all real-time media processing functions. All resources supported within the PNX8526 are accessible by both the MIPS processor and the TM32 CPU. The software documentation of the PNX8526 provides more details on the interaction between the MIPS and the TM32 CPU. The PNX8526 is intended to be used with a small companion IC, the PNX8510. This analog companion chip provides the majority of analog video and audio support for the output of the PNX8526. The PNX8510 companion is capable of simultaneously driving two video channels (six DACs) and two stereo audio channels (four DACs). 1 page Philips Semiconductors PNX8526 Programmable source decoder with integrated peripherials Table 2: Peripheral Controller Interface (PCI) …continued # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol Pin Type Description Alternate function PCI_AD[21] AE4 I/O multiplexed address or data bit 21 PCI_AD[20] AD4 I/O multiplexed address or data bit 20 PCI_AD[19] AE5 I/O multiplexed address or data bit 19 PCI_AD[18] AD5 I/O multiplexed address or data bit 18 PCI_AD[17] AC5 I/O multiplexed address or data bit 17 PCI_AD[16] AC6 I/O multiplexed address or data bit 16 PCI_AD[15] AD8 I/O multiplexed address or data bit 15 PCI_AD[14] AC8 I/O multiplexed address or data bit 14 PCI_AD[13] AF9 I/O multiplexed address or data bit 13 PCI_AD[12] AE9 I/O multiplexed address or data bit 12 PCI_AD[11] AD9 I/O multiplexed address or data bit 11 PCI_AD[10] AC9 I/O multiplexed address or data bit 10 PCI_AD[9] AF10 I/O multiplexed address or data bit 9 PCI_AD[8] AE10 I/O multiplexed address or data bit 8 PCI_AD[7] AC10 I/O multiplexed address or data bit 7 PCI_AD[6] AF11 I/O multiplexed address or data bit 6 PCI_AD[5] AE11 I/O multiplexed address or data bit 5 PCI_AD[4] AD11 I/O multiplexed address or data bit 4 PCI_AD[3] AC11 I/O multiplexed address or data bit 3 PCI_AD[2] AE12 I/O multiplexed address or data bit 2 PCI_AD[1] AD12 I/O multiplexed address or data bit 1 PCI_AD[0] AC12 I/O multiplexed address or data bit 0 PCI_CBE[3] AD1 I/O multiplexed command or byte enable 3 PCI_CBE[2] AF5 I/O multiplexed command or byte enable 2 PCI_CBE[1] AE8 I/O multiplexed command or byte enable 1 PCI_CBE[0] AD10 I/O multiplexed command or byte enable 0 CLK AA1 I PCI bus clock PCI_DEVSEL AF7 I/O device select is asserted when a target address is decoded and remains asserted to indicate that a target device is selected PCI_FRAME AF6 I/O frame is asserted to indicate start of bus transaction and remains asserted until ﬁnal data phase begins PCI_GNT Y3 I/O arbitration grant is asserted to indicate access to the bus has been granted; this pin is an input when an external arbiter is used and an output when using the internal arbiter PCI_GNT_A Y4 I/O auxiliary arbitration PCI_GNT_A is asserted to indicate bus access has been granted to an external PCI master; used where internal arbiter is conﬁgured # 9397 750 15101 Product data sheet Rev. 02 — 11 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 5 of 65 5 Page Philips Semiconductors PNX8526 Programmable source decoder with integrated peripherials 9397 750 15101 Product data sheet Table 7: Universal Serial Bus (USB) …continued Symbol Pin Type Description USB_OVRCUR W2 I indicates over current being drawn by a USB device 0 = over current detected 1 = no over current Table 8: IEEE 1394 port Symbol Pin Type PHY_D[7] B9 I/O PHY_D[6] D10 I/O PHY_D[5] C9 I/O PHY_D[4] A8 I/O PHY_D[3] B8 I/O PHY_D[2] D9 I/O PHY_D[1] C8 I/O PHY_D[0] A7 I/O PHY_CTL[1] B7 I/O PHY_CTL[0] C7 I/O PHY_LREQ B5 O PHY_ISO_N A6 I CLK_L1394 D8 I Description PHY data bit 7; data is expected on ports 7:0 for 400 MB packets PHY data bit 6; data is expected on ports 7:0 for 400 MB packets PHY data bit 5; data is expected on ports 7:0 for 400 MB packets PHY data bit 4; data is expected on ports 7:0 for 400 MB packets PHY data bit 3; data is expected on ports 3:0 for 200 MB packets PHY data bit 2; data is expected on ports 3:0 for 200 MB packets PHY data bit 1; data is expected on ports 1:0 for 100 MB packets PHY data bit 0; data is expected on ports 1:0 for 100 MB packets PHY control bit 1; indicates the mode for data on the Din port PHY control bit 0; indicates the mode for data on the Din port used by the link to make bus requests and to access PHY registers; this is a serial bus; a train of pulses is sent on this signal signals which type of isolation mode is used at the PHY-Link interface 0 = this is 1394-1995 annex J type isolation; enables differentiator circuitry 1 = direct connection or single capacitor isolation mode; this will disable the differentiator circuitry system clock. 49.152 MHz input Table 9: Serial communication port (I2C-bus) Symbol Pin Type Description I2C1_SCL D6 I/O serial communications port (I2C-bus) clock I2C1_SDA A4 I/O serial communications port (I2C-bus) data I2C2_SCL H1 I/O serial communications port (I2C-bus) clock I2C2_SDA K4 I/O serial communications port (I2C-bus) data Table 10: Audio and video interface # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol Pin Type Description DV_OUT1[9] DV_OUT1[8] DV_OUT1[7] M2 O M1 O N4 O digital video output1; bit 9 for primary display channel from AICP digital video output1; bit 8 for primary display channel from AICP digital video output1; bit 7 for primary display channel from AICP Alternate function Rev. 02 — 11 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 11 of 65 11 Page

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