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PDF H8S2149 Data sheet ( Hoja de datos )
| Número de pieza | H8S2149 | |
| Descripción | (H8S2149 / H8S2169) Hitachi 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de H8S2149 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Preface
The H8S/2149 and H8S/2169 F-ZTAT™ comprises high-performance microcomputers with a 32-
bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system
configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen
internal 16-bit general registers with a 32-bit configuration, and a concise and optimized
instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
Programs based on the high-level language C can also be run efficiently.
Single-power-supply flash memory (F-ZTAT™*) is available, providing a quick and flexible
response to conditions from ramp-up through full-scale volume production, even for applications
with frequently changing specifications.
On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR),
watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface
(SCI, IrDA), I2C bus interface (IIC), PS/2-compatible keyboard buffer controller, host interface
(HIF:XBS and LPC), D/A converter (DAC), A/D converter (ADC), and I/O ports.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
Use of the H8S/2149 and H8S/2169 F-ZTAT™ enables compact, high-performance systems to be
implemented easily. The comprehensive PC-related interface functions and 16 × 8 matrix key-
scan functions are ideal for applications such as notebook PC keyboard control and intelligent
battery and power supply control. In particular, the provision of two on-chip host interfaces—a
conventional X-BUS (ISA) interface and an LPC interface (a new standard)—provide flexible
support for PC systems in a period of transition.
This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the
instruction set.
This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Although the
H8S/2169 is not explicitly mentioned in Section 2 to 7 or Section 9 to 22, the descriptions in these
Sections apply to both the H8S/2149 and H8S/2169.
Note: * F-ZTAT™ (Flexible-ZTAT) is a trademark of Hitachi, Ltd.
5 Page 
Page
520
521
523, 524
526
527
529, 530
538
557
572
587
589
596 to 603
610
616
618, 619
627
634
645
Item
Revision (See Manual for Details)
16.3.10 Sample Flowcharts Figure 16.14 Flowchart for Master Transmit Mode
Completely amended
Figure 16.15 Flowchart for Master Receive Mode
Completely amended
16.3.11 Initialization of
Internal State
Notes on Initialization: Description amended
16.4 Usage Notes
Table 16.7 Permissible SCL Rise Time Values
φ = 16 MHz or more deleted
Table16.8 I2C Bus Timing
φ = 16 MHz or more deleted
Notes on start condition Issuance for Retransmission
Notes on I2C Bus Interface Stop Condition Instruction
Issuance added
17.2.4 Module Stop Control Added
Register
18A.2.1 System Control
Register
Bit 1: Description amended
18A.5 Usage Note
(2) Data contention on the host interface data bus (HDB)
added
18B.2.3 Host Interface
HICR2 bits 3 to 0: Description amended when IBFIE3 is
Control Registers 2 and 3 set to 1
18B.2.4 LPC Channel 3
Address Register
LADR3L bit 2: Description amended
18B.2.9 SERIRQ Control Names of SERIRQ interrupt sources amended
Registers
18B.3.4 Host Interface
Shutdown Function
Table 18B.5 Scope of HIF Pin Shutdown
CLKRUN I/O amended
Note added
18B.4.1 IBF1, IBF2, IBF3, Table 18B.7 Receive Complete Interrupts are Error
ERRI
interrupt
IBF3 description amended
18B.5 Usage Note
(3) added
20.1.1 Features
Conversion time amended
20.2.3 A/D Control Register Bits 5 to 0: Description amended
20.6 Usage Notes
Table 20.5 Analog Pin Ratings
Permissible signal source impedance max. value
amended
Note added
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet H8S2149.PDF ] | |
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