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AD6652 PDF Data sheet ( 特性 )

部品番号 AD6652
部品説明 12-Bit / 65 MSPS IF to Baseband Diversity Receiver
メーカ Analog Devices
ロゴ Analog Devices ロゴ 


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AD6652 Datasheet, AD6652 PDF,ピン配置, 機能
12-Bit, 65 MSPS
IF to Baseband Diversity Receiver
AD6652
FEATURES
SNR = 90 dB in 150 kHz bandwidth (to Nyquist
@ 61.44 MSPS)
Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)
Integrated dual-channel ADC:
Sample rates up to 65 MSPS
IF sampling frequencies to 200 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range (1 V to 2 V p-p)
Differential analog inputs
ADC clock duty cycle stabilizer
85 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC):
Crossbar switched DDC inputs
Digital resampling for noninteger decimation
Programmable decimating FIR filters
Flexible control for multicarrier and phased array
Dual AGC stages for output level control
Dual 16-bit parallel or 8-bit link output ports
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers:
GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,
IS95, IS136, CDMA2000, IMT-2000
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Instrumentation and test equipment
FUNCTIONAL BLOCK DIAGRAM
DUAL-CHANNEL 12-BIT A/D FRONT END
WIDEBAND DIGITAL DOWNCONVERTER (DDC)
VINA+
VINA–
SHA
REFTA
REFBA
VREF
SENSE
REFTB
REFBB
VINB+
VINB–
SHA
ADC 12 CHANNEL A
CHANNEL /
A
OTRA
LIA
LIA
VREF
PSEUDO
RANDOM
NOISE
SEQUENCE
LIB
LIB
OTRB
ADC 12
CHANNEL /
B CHANNEL B
RCIC2
RESAMPLER
CIC5
NCO
RCIC2
RESAMPLER
CIC5
NCO
RCIC2
RESAMPLER
CIC5
NCO
RCIC2
RESAMPLER
CIC5
NCO
RAM
COEF.
FILTER
CHANNEL 0
RAM
COEF.
FILTER
CHANNEL 1
RAM
COEF.
FILTER
CHANNEL 2
RAM
COEF.
FILTER
CHANNEL 3
TO OUTPUT PORTS
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
TO OUTPUT PORTS
AGC A*
TO OUTPUT
PORTS
AGC B*
TO OUTPUT PORTS
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
PORT A
8-BIT DSP
LINK
OR
16-BIT
PARALLEL
OUTPUT
CONTROL
OUTPUT
MUX
CIRCUITRY
PORT B
8-BIT DSP
LINK
OR
16-BIT
PARALLEL
OUTPUT
PDWN
SHRDREF
MODE ACLK
SELECT DUTYEN
CLOCK
DUTY
CYCLE
STABILIZER
SYNCA
SYNCB
SYNCC
SYNCD
EXTERNAL
SYNC.
CIRCUIT
*DATA INTERLEAVING AND INTERPOLATING HB FILTER CONTROL
DDC
CLK
BUILT-IN
SELF-TEST
CIRCUITRY
PROGRAM
MICROPORT
8 33
+3.0AVDD
+3.3VDDIO
2.5VDD
AGND
DGND
CLK
DATA CONT ADD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

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